參數(shù)資料
型號: MC68HC05PD6
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 36/165頁
文件大?。?/td> 841K
代理商: MC68HC05PD6
GENERAL RELEASE SPECIFICATION
July 7, 1997
MOTOROLA
P-DECODER
MC68HC05PD6
12-14
REV 1.1
A17-A0 is the 18-bit user dened address.
AFNS
0 =
The value in FA is assigned to address A. User address, A17-A0, is
compared to the frame number specied in FA of the incoming data.
1 =
The values in FB is assigned to address A. User address, A17-A0, is
compared to the frame numbers specied in FB of the incoming
data.
NOTE
If less than 6 user addresses are used, say only 3 user addresses
are used, the 3 unused addresses must be written with the same
values as any of the addresses used. For example, if address A =
000008, B = 801AA3, D = 016913, then address C, E, F should be
written to 000008, 016913 and 016913 respectively or both written
to 000008 or etc...
W
R
ADRA0
$0014
reset
A7
0
7
00
54
0
0000
6
3210
A6
A3
A2
A1
A0
A5
A4
option
map
W
R
ADRA1
$0015
reset
A15
0
7
00
54
0
0000
6
3210
A14
A11
A10
A9
A8
A13
A12
option
map
W
R
ADRA2
$0016
reset
AFNS
0
7
00
54
0
0000
6
3210
0
A17
A16
00
option
map
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