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參數(shù)資料
| 型號： | MC68HC05L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 42/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC05L1B |
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MOTOROLA
5-8
MC68HC05L1
PROGRAMMABLE TIMER
5
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide range of applications including xed
frequency generation.
A software force compare will affect the corresponding output pin TCMP1 and/or TCMP2, but will
not affect the compare ag, thus it will not generate an interrupt.
5.4
Timer Control and Status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
5.4.1
Timer Control Register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
ICIE - Input Capture Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status ag (in the Timer
Status register) is set.
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status ag (in the Timer
Status register) is set.
1 (set)
–
Output Compare interrupt enabled.
0 (clear) –
Output Compare interrupt disabled.
TOIE - Timer Overow Interrupt Enable
If this bit is set, a timer interrupt is enabled whenever the TOF status ag (in the Timer Status
register) is set.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer control (TCR)
$0012
ICIE
OCIE
TOIE
FOLV2 FOLV1 OLV2
IEDG1 OLVL1 0000 00u0
TPG
42
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