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| 型號(hào)： | MC68HC05F8FU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 74/126頁(yè) |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8FU |
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MC68HC05F8
MOTOROLA
6-3
TIMERS
6
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by two prescalers. The rst stage programmable prescaler provides a slow timer clock
by dividing the internal processor clock either by 1, 4, 8, or 16. The second stage is a xed divide
by four prescaler. See Figure 6-1 and Table 6-1 for prescaler values. The counter is incremented
during the low portion of the internal bus clock, and the counting can be inhibited by setting the
TIMHA bit in the Event Enable register (bit 7 of address $16). Software can read the counter at
any time without affecting its value.
The double-byte, free-running counter can be read from either of two locations, $1E & $1F
(counter register) or $20 & $21 (counter alternate register). Reading only the least signicant byte
(LSB) of the free-running counter ($1F or $21) receives the count value at the time of the read. If
the most signicant byte (MSB) ($1E or $20) is read rst, the LSB ($1F or $21) is transferred to a
buffer. This buffer value remains xed after the rst MSB read, even if the MSB is read several
times. This buffer is accessed when the LSB ($1F or $21) is read, and thus, completes a read
sequence of the complete counter value.
Reading the timer counter register low byte after reading the timer status register clears the timer
overow ag (TOF), but reading the counter alternate register does not affect TOF. Therefore, the
counter alternate register can be read any time without risk of missing timer overow interrupts
due to a cleared TOF.
The free-running counter is preset to $FFFC during reset and is always a read-only register.
During a power-on reset, the counter is also preset to $FFFC and begins running after the
oscillator start-up delay. The value in the free-running counter repeats every (262144
÷R
TB)
internal bus clock cycles (tCYC). RTB is the ratio of timer clock to bus clock frequency, and is
dependent on the values of TCSA0 and TCSA1 bits. TOF is set when the counter overows (from
$FFFF to $0000); this will cause an interrupt if TOIE in the Timer Control register is set (bit 5 of
address $18).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System Option Register
$35
-
TCSA1 TCSA0 INTN1 INTN2
-
-000 0---
Table 6-1 Timer A Clock Frequency Selection
TCSA1
TCSA0
Clock Frequency of Timer A
0
E/4
0
1
E/16
1
0
E/32
1
E/64
Where E = internal bus clock
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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