參數(shù)資料
型號： MC68HC05C0P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 5/96頁
文件大?。?/td> 357K
代理商： MC68HC05C0P
MOTOROLA
Section 1: Introduction
Page 4
MC68HC05C0 Specification Rev. 1.2
1.4.7
AS (ADDRESS STROBE)/ CS2
In Muxed mode, this pin is the active high Address Strobe, which is used to indicate the
presence of the lower address byte on the muxed address/data bus. See Section 9
ADDRESS/DATA BUS INTERFACE for the timing and a detailed description of the address
strobe. In Non-Muxed mode, this active low pin becomes an active low chip select. See
Section 8 SYSTEM CONFIGURATION for more information on the chip selects.
1.4.8
RD
This active low output pin is used to drive an external peripheral during an external read
cycle. It can also indicate an internal read cycle if Internal Read Visibility is selected in the
Configuration Register. See Section 9 ADDRESS/DATA BUS INTERFACE for the timing
and a detailed description of the RD signal.
1.4.9
WR
This active low output pin is used to drive an external peripheral during an external write
cycle. It can also indicate an internal write cycle if Internal Read Visibility is selected in the
Configuration Register. See Section 9 ADDRESS/DATA BUS INTERFACE for the timing
and a detailed description of the WR signal.
1.4.10
A7-A0/PD7-PD0
These eight I/O lines constitute either the lower address byte or Port D. In Non-Muxed
mode, they are dedicated to the lower address byte. See Section 9 ADDRESS/DATA BUS
INTERFACE for the timing and a detailed description of the address bus. In Muxed mode,
they are Port D. The state of any Port D pin is software programmable and all Port D lines
are configured as inputs during Reset. See Section 7.4 INPUT/OUTPUT PROGRAMMING
for a detailed description of I/O programming. Port D also can be programmed to enable
internal pullups and generate an interrupt when any of the 8 I/O lines are pulled low. This
can be used as a keyboard scan. See Section 7.3 PORT D for more details.
1.4.11
PB4-PB0/SCK,TDO,RDI,TCAP,TCMP
These five I/O lines constitute Port B and are shared with internal peripherals. The state of
any pin is software programmable and all Port B lines are configured as inputs during
Reset. See Section 7.4 INPUT/OUTPUT PROGRAMMING for a detailed description of
I/
O programming. Signals SCK,TDO and RDI of the SCI subsystem are shared with PB4,
description of the SCI. Signals TCAP and TCMP of the 16-Bit Timer are shared with PB1
and PB0. See Section 11 16-BIT TIMER for a detailed description of the 16-Bit Timer. PB0
has a high current sink and source capability.
1.4.12
CS1/PB5
This pin can be used as a dedicated chip select or as an additional Port B line (PB5). See
Section 8 SYSTEM CONFIGURATION for more information on the chip selects. If it is used
as a Port B line, it will function identically to PB4-PB0. See Section 7.4 INPUT/OUTPUT
PROGRAMMING for a detailed description of I/O programming.
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