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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC68EC030CFE25C |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 7/36闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU 32BIT ENH 25MHZ 132-CQFP |
| 妯�(bi膩o)婧栧寘瑁濓細 | 36 |
| 绯诲垪锛� | M680x0 |
| 铏曠悊鍣ㄩ鍨嬶細 | M680x0 32-浣� |
| 閫熷害锛� | 25MHz |
| 闆诲锛� | 5V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 132-BCQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 132-CQFP锛�24x24锛� |
| 鍖呰锛� | 鎵樼洡 |
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MOTOROLA
MC68EC030 TECHNICAL DATA
1 5
SYNCHRONOUS TRANSFERS
Synchronous bus cycles are terminated by asserting
STERM, which automatically indicates that the bus
transfer is for 32 bits. Since this input is not synchronized internally, two-clock-cycle bus accesses can be
performed if the signal is valid one clock after the beginning of the bus cycle with the appropriate setup
time. However, the bus cycle may be lengthened by delaying
STERM (inserting wait states in one-clock
increments) until the device being accessed is able to terminate the cycle. After the assertion of
STERM,
these cycles may be aborted upon the assertion of
BERR, or they may be retried with the simultaneous
assertion of
BERR and HALT.
BURST READ CYCLES
The MC68EC030 provides support for burst filling of its on-chip instruction and data caches, adding to
the overall system performance. The on-chip caches are organized with a line size of four long words;
there is only one tag for the four long words in a line. Since locality of reference is present to some
degree in most programs, filling of all four entries when a single entry misses can be advantageous,
especially if the time spent filling the additional entries is minimal. When the caches are burst filled, data
can be latched by the controller in as little as one clock for each 32 bits. Burst read cycles can be
performed only when the MC68EC030 requests them (with the assertion of
CBREQ) and only when the
first cycle is a synchronous cycle as previously described. If the cache burst acknowledge (
CBACK) input
is valid at the appropriate time in the synchronous bus cycle, the controller keeps the original
AS, DS,
R/
W, address, function code, and size outputs asserted and latches 32 bits from the data bus at the end
of each subsequent clock cycle that has
STERM asserted. This procedure continues until the burst is
complete (the entire block has been transferred),
BERR is asserted in lieu of or after STERM, the cache
inhibit in (
CIIN) input is asserted, or the CBACK input is negated. The cache preloading allowed by the
bursting enables the MC68EC030 to take advantage of cost-effective DRAM technology with minimal
performance impact.
EXCEPTIONS
The types of exceptions and the exception processing sequence are discussed in the following
paragraphs.
TYPES OF EXCEPTIONS
Exceptions can be generated by either internal or external causes. The externally generated exceptions
are interrupts,
BERR, and RESET. Interrupts are requests from peripheral devices for controller action;
whereas,
BERR and RESET are used for access control and controller restart. The internally generated
exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPVcc, cpTRAPcc, CKH, CKH2, and DIV instructions can all generate exceptions as part of instruction
execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is
processed. The other internally generated exceptions are caused by illegal instructions, instruction
fetches from odd addresses, and privilege violations.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATF16V8C-7SU | IC PLD EE 7.5NS 20-SOIC |
| ATF22LV10C-10PU | IC PLD 10NS 24DIP |
| AMC49DTEI | CONN EDGECARD 98POS .100 EYELET |
| MC68030FE25C | IC MPU 32BIT ENHANCED 132-CQFP |
| MC68030FE20C | IC MPU 32BIT ENHANCED 132-CQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC68EC030FE25B | 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪: |
| MC68EC030FE25C | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B ON-CHIP CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68EC030FE25CB1 | 鍔熻兘鎻忚堪:IC MPU 32BIT ENH 25MHZ 132-CQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰檿鐞嗗櫒 绯诲垪:M680x0 妯�(bi膩o)婧栧寘瑁�:1 绯诲垪:MPC85xx 铏曠悊鍣ㄩ鍨�:32-浣� MPC85xx PowerQUICC III 鐗归粸:- 閫熷害:1.2GHz 闆诲:1.1V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:783-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:783-FCPBGA锛�29x29锛� 鍖呰:鎵樼洡 |
| MC68EC030FE40B | 鍒堕€犲晢:Motorola Inc 鍔熻兘鎻忚堪: |
| MC68EC030FE40C | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B ON-CHIP CACHE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
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