- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4081 > MC68EC000EI8 (Freescale Semiconductor)IC MPU 32BIT 85MHZ 68-PLCC PDF資料下載
參數(shù)資料
| 型號： | MC68EC000EI8 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/26頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 85MHZ 68-PLCC |
| 標準包裝： | 18 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 8MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（25x25） |
| 包裝： | 管件 |
13
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued)
Applies to 3.3V and 5V.
NOTES: 1.
For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2.
Actual value depends on clock period.
3.
If #47 is satised for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4.
For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the
system is powered up, #56 refers to the minimum pulse width required to reset the controller.
5.
If the asynchronous input setup time (#47) requirement is satised for DTACK, the DTACK asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6.
When AS and R/W are equally loaded (
±20%), subtract 5 ns from the values given in these columns.
7.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
NUM
CHARACTERISTIC
10MHz
16MHz
20MHz
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
29
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read)
0—0—0—
ns
29A
AS, LDS, UDS Negated to Data-In High Impedance (Read)
—
150
—
90
—
75
ns
30
AS, LDS, UDS Negated to BERR Negated
0—0—0—
ns
312,5
DTACK Asserted to Data-In Valid (Setup Time on Read)
—
65
—
50
—
42
ns
32
HALT and RESET Input Transition Time
0
150
0
150
0
150
ns
33
Clock High to BG Asserted
—
35
—
30
—
25
ns
34
Clock High to BG Negated
—
35
—
30
—
25
ns
35
BR Asserted to BG Asserted
1.5
3.5
1.5
3.5
1.5
3.5
Clks
367
BR Negated to BG Negated
1.5
3.5
1.5
3.5
1.5
3.5
Clks
38
BG Asserted to Control, Address, Data Bus High Impedance (AS
Negated)
—55—50—42
ns
39
BG Width Negated
1.5
—
1.5
—
1.5
—
Clks
44
AS, LDS, UDS Negated to AVEC Negated
0
55
0
50
0
42
ns
475
Asynchronous Input Setup Time
5—5—5—
ns
482,3
BERR Asserted to DTACK Asserted
20
—
10
—
10
—
ns
52
Data-In Hold from Clock High
0—0—0—
ns
53
Data-Out Hold from Clock High (Write)
0—0—0—
ns
55
R/W Asserted to Data Bus Impedance Change (Write)
20
—
10
—
0
—
ns
564
HALT, RESET Pulse Width
10
—
10
—
10
—
Clks
587
BR Negated to AS, LDS, UDS, R/W Driven
1.5
—
1.5
—
1.5
—
Clks
58A7
BR Negated to FC Driven
1—1—1—
Clks
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT7024L20PFI8 | IC SRAM 64KBIT 20NS 100TQFP |
| MPC8309VMAFDCA | IC PROCESSOR E300 489MAPBGA |
| MPC8306SCVMADDCA | IC PROCESSOR E300 369MAPBGA |
| MPC8308ZQAFD | MPU POWERQUICC II PRO 473MAPBGA |
| AMM43DRMI-S288 | CONN EDGECARD 86POS .156 EXTEND |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68EC000EI8 | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC68EC000EI8R2 | 功能描述:微處理器 - MPU 8/16/32 BIT MPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68EC000FN10 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Addendum to M68000 User Manual |
| MC68EC000FN12 | 制造商:Motorola Inc 功能描述: |
| MC68EC000FN12R2 | 制造商:Rochester Electronics LLC 功能描述:8/16/32 BIT MPU - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。