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參數(shù)資料
| 型號： | MC68EC000CAA20 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 20MHZ 64-QFP |
| 標準包裝： | 84 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 20MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-QFP |
| 供應商設備封裝： | 64-QFP（14x14） |
| 包裝： | 托盤 |
6
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the
processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit.
This can be done, but be careful that runt clocks and spurious glitches are not presented to the
MC68SEC000. A timing diagram is shown in Figure 4.
Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus
Note: While the MC68SEC000 is in the low-power mode, all inputs must be driven to VDD or VSS, or have a
pull-up or pull-down resistor.
3.
This step is optional depending on whether your applications require the MC68SEC000 signals with
three-state capability to be placed into a high-impedance state. To place the MC68SEC000 into a
three-state condition, the proper method for arbitrating the bus (as described in 5.2 Bus Arbitration
in the
M68000 User’s Manual, Rev 8) should be completed during the fetch of the status register data
for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5.
Figure 5. MC68SEC000 Clock Stop Timing with Bus Arbitration for 16-Bit Data Bus
Write to
Low-Power
Address
Fetch Immediate
Data of STOP
Instruction
Stop
CLK
S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
DTACK
RW
AS
BR
BG
CLK
S0 S1 S2 S3 S4 S5 S6 S7
CPU_CLK
DTACK
RW
AS
Write to
Low-Power
Address
Fetch Immediate
Data of STOP
Instruction
Stop
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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