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| 型號： | MC68EC000AA16R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 22/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 16MHZ 64-QFP |
| 標準包裝： | 750 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 16MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-QFP |
| 供應商設備封裝： | 64-QFP（14x14） |
| 包裝： | 帶卷 (TR) |
5
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
power consumption to its quiescent value1 while maintaining the internal state of the processor. The
low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided
by Motorola.
To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A
recommended method for entering the low-power mode is to use the TRAP instruction, which causes the
processor to begin exception processing, thus entering the supervisor mode. External circuitry should
accomplish the following steps during the trap routine:
1.
Externally detect a write to the low-power address. You select this address which can be any address
in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be
detected by polling A23–A0, R/W, and FC2–FC0. When the low-power address is detected, R/W is
a logic low, and the function codes have a five (101) on their output, the processor is writing to the
low-power address in supervisor mode and user-designed circuitry should assert the
Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus
2.
number of bus cycles starting with the write to the low-power address and will stop the processor
clock on the first falling edge of the system clock after the bus cycle that reads the immediate data
1. The preliminary specication for the MC68SEC000’s current drain while in the low-power mode is Idd < 2
A for 3.3V operation and
Idd < 5
A for 5.0V operation.
Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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