參數(shù)資料
型號(hào): MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁(yè)數(shù): 66/133頁(yè)
文件大?。?/td> 798K
代理商: MC68CK338
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MOTOROLA
66
MC68CK338
MC68CK338TS/D
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register. The QSM has read-only access.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device and only responds to externally generated serial data.
1 = QSPI is system master and can initiate transmission to external SPI devices.
MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and
may only be written by the CPU.
WOMQ — Wired-OR Mode for QSPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
WOMQ allows the wired-OR function to be used on QSPI pins, regardless of whether they are used as
general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins regardless of whether the
QSPI is enabled or disabled.
BITS[3:0] — Bits Per Transfer
In master mode, when BITSE in a command is set, the BITS[3:0] field determines the number of data
bits transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits.
In slave mode, the command RAM is not used and the setting of BITSE has no effect on QSPI transfers.
Instead, the BITS[3:0] field determines the number of bits the QSPI will receive during each transfer be-
fore storing the received data.
Table 41
shows the number of bits per transfer.
SPCR0 —
QSPI Control Register 0
$YFFC18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSTR
WOMQ
BITS[3:0]
CPOL
CPHA
SPBR[7:0]
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
Table 41 Bits Per Transfer
BITS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits Per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
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