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參數(shù)資料
| 型號： | MC68CK331CAG16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲(chǔ)器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
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MC68331TS/D
3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Perform a software watchdog service sequence as follows:
1.
Write $55 to SWSR.
2.
Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
3.2.7 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] —Periodic Interrupt Request Level
The following table shows what interrupt request level is asserted when a periodic interrupt is generat-
ed. If a PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT in-
terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled.
SWSR —Software Service Register
$YFFA27
15
8
7
6
5
4
3
2
1
0
NOT USED
0
RESET:
0
MODCLK
SWP
01
10
PICR — Periodic Interrupt Control Register
$YFFA22
15
14
13
12
11
10
8
7
0
PIRQL
PIV
RESET:
0
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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