參數(shù)資料
型號(hào): MC68334GCEH16
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 19/76頁(yè)
文件大?。?/td> 0K
描述: IC MCU 16MHZ 2K RAM 132-PQFP
標(biāo)準(zhǔn)包裝: 36
系列: M683xx
核心處理器: CPU32
芯體尺寸: 32-位
速度: 16MHz
連通性: EBI/EMI,UART/USART
輸入/輸出數(shù): 47
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 132-BQFP 緩沖式
包裝: 托盤
MC68334
26
MC68334TS/D REV. 1
Autovector signal (AVEC) can terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates
that the MCU will internally generate a vector number to locate an interrupt handler routine. If it is con-
tinuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored
during all other bus cycles.
3.4.8 Data Transfer Mechanism
The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge
inputs (DSACK1 and DSACK0).
3.4.9 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0
and DSACK1 inputs, as shown in the following table.
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-
ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-
nated as shown in the following figure. OP0 is the most significant byte of a long-word operand, and
OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and
OP1. The single byte of a byte-length operand is OP0.
Figure 9 Operand Byte Order
Table 11 Effect of DSACK Signals
DSACK1
DSACK0
Result
1
Insert Wait States in Current Bus Cycle
1
0
Complete Cycle — Data Bus Port Size is 8 Bits
0
1
Complete Cycle — Data Bus Port Size is 16 Bits
0
Reserved
Operand
Byte Order
31
24
23
16
15
8
7
0
Long Word
OP0
OP1
OP2
OP3
Three Byte
OP0
OP1
OP2
Word
OP0
OP1
Byte
OP0
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MC68334GCEH16 制造商:Freescale Semiconductor 功能描述:Microcontroller
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