參數(shù)資料
型號： MC68332GCPV20
廠商： Freescale Semiconductor
文件頁數(shù)： 48/88頁
文件大小： 0K
描述： IC MCU 32BIT 20MHZ GMASK 144LQFP
標準包裝： 60
系列： M683xx
核心處理器： CPU32
芯體尺寸： 32-位
速度： 20MHz
連通性： EBI/EMI，SCI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
包裝： 托盤
MOTOROLA
MC68332
52
MC68332TS/D
5 Time Processor Unit
The time processor unit (TPU) provides optimum performance in controlling time-related activity. The
TPU contains a dedicated execution unit, a tri-level prioritized scheduler, data storage RAM, dual-time
bases, and microcode ROM. The TPU controls 16 independent, orthogonal channels, each with an as-
sociated I/O pin, and is capable of performing any microcoded time function. Each channel contains
dedicated hardware that allows input or output events to occur simultaneously on all channels.
Figure 12 TPU Block Diagram
5.1 MC68332 and MC68332A Time Functions
The following paragraphs describe factory-programmed time functions implemented in standard and
enhanced standard TPU microcode ROM. A complete description of the functions is beyond the scope
of this summary. Refer to
Using the TPU Function Library and TPU Emulation Mode (TPUPN00/D) as
well as other TPU programming notes for more information about specific functions.
5.1.1 Discrete Input/Output (DIO)
When a pin is used as a discrete input, a parameter indicates the current input level and the previous
15 levels of a pin. Bit 15, the most significant bit of the parameter, indicates the most recent state. Bit
14 indicates the next most recent state, and so on. The programmer can choose one of the three fol-
lowing conditions to update the parameter: 1) when a transition occurs, 2) when the CPU makes a re-
quest, or 3) when a rate specified in another parameter is matched. When a pin is used as a discrete
output, it is set high or low only upon request by the CPU.
T2CLK
PINS
SERVICE REQUESTS
DATA
TCR1
TCR2
MICROENGINE
CONTROL
STORE
EXECUTION
UNIT
I M B
PARAMETER
RAM
CHANNEL
CONTROL
DEVELOPMENT
SUPPORT AND TEST
SYSTEM
CONFIGURATION
SCHEDULER
CONTROL AND DATA
CONTROL
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
CHANNEL 15
CHANNEL
DATA
TPU BLOCK
HOST
INTERFACE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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