參數(shù)資料
    型號(hào): MC68332GCPV16B1
    廠商: Freescale Semiconductor
    文件頁數(shù): 27/88頁
    文件大?。?/td> 0K
    描述: IC MCU 32BIT 16MHZ 144-LQFP
    標(biāo)準(zhǔn)包裝: 300
    系列: M683xx
    核心處理器: CPU32
    芯體尺寸: 32-位
    速度: 16MHz
    連通性: EBI/EMI,SCI,SPI,UART/USART
    外圍設(shè)備: POR,PWM,WDT
    輸入/輸出數(shù): 15
    程序存儲(chǔ)器類型: ROMless
    RAM 容量: 2K x 8
    電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 144-LQFP
    包裝: 托盤
    MC68332
    MOTOROLA
    MC68332TS/D
    33
    3.5.3 Base Address Registers
    A base address is the starting address for the block enabled by a given chip select. Block size deter-
    mines the extent of the block above the base address. Each chip select has an associated base register
    so that an efficient address map can be constructed for each application. If a chip-select base address
    register is programmed with the same address as a microcontroller module or memory array, an access
    to that address goes to the module or array and the chip-select signal is not asserted.
    ADDR[23:11] — Base Address Field
    This field sets the starting address of a particular address space. The address compare logic uses only
    the most significant bits to match an address within a block. The value of the base address must be a
    multiple of block size. Base address register diagrams show how base register bits correspond to ad-
    dress lines.
    BLKSZ — Block Size Field
    This field determines the size of the block that must be enabled by the chip select. The following table
    shows bit encoding for the base address registers block size field.
    3.5.4 Option Registers
    The option registers contain eight fields that determine timing of and conditions for assertion of chip-
    select signals. For a chip-select signal to be asserted, all bits in the base address register must match
    the corresponding internal upper address lines, and all conditions specified in the option register must
    be satisfied. These conditions also apply to providing DSACK or autovector support.
    CSBARBT — Chip-Select Base Address Register Boot ROM
    $YFFA48
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    0
    ADDR
    23
    ADDR
    22
    ADDR
    21
    ADDR
    20
    ADDR
    19
    ADDR
    18
    ADDR
    17
    ADDR
    16
    ADDR
    15
    ADDR
    14
    ADDR
    13
    ADDR
    12
    ADDR
    11
    BLKSZ
    RESET:
    0
    1
    CSBAR[10:0] —Chip-Select Base Address Registers
    $YFFA4C–$YFFA74
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    0
    ADDR
    23
    ADDR
    22
    ADDR
    21
    ADDR
    20
    ADDR
    19
    ADDR
    18
    ADDR
    17
    ADDR
    16
    ADDR
    15
    ADDR
    14
    ADDR
    13
    ADDR
    12
    ADDR
    11
    BLKSZ
    RESET:
    0
    Block Size Field
    Block Size
    Address Lines Compared
    000
    2 K
    ADDR[23:11]
    001
    8 K
    ADDR[23:13]
    010
    16 K
    ADDR[23:14]
    011
    64 K
    ADDR[23:16]
    100
    128 K
    ADDR[23:17]
    101
    256 K
    ADDR[23:18]
    110
    512 K
    ADDR[23:19]
    111
    1 M
    ADDR[23:20]
    F
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    Freescale Semiconductor, Inc.
    For More Information On This Product,
    Go to: www.freescale.com
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