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MOTOROLA
D-40
REGISTER SUMMARY
MC68331
USER’S MANUAL
D
Table D-18 Register Bit and Field Mnemonics
Mnemonic
ADDR[23:11]
AVEC
BITS
BITSE
BLKSZ
BME
BMT[1:0]
BYTE
C
CONT
CPHA
CPOL
CPROUT
CPR[2:0]
CPTQP
CSPA0[6:1]
CSPA1[4:0]
CSBOOT
DDE[7:0]
DDF[7:0]
DDRGP[7:0]
DDQS[7:0]
DSACK
DSCK
DSCKL
DT
DTL
EDGE[4:1]
EDIV
ENDQP
EXOFF
EXT
F1A
F1B
FE
FOC[5:1]
FPWMA
FPWMB
FRZBM
FRZSW
FRZ[1:0]
FRZ[1:0]
HALT
HALTA
HLT
HME
HMIE
Name
Register Location
CSBAR[0:10], CSBARBT
CSOR[0:10], CSORBT
SPCR0
CR[0:F]
CSBAR[0:10], CSBARBT
SYPCR
SYPCR
CSOR[0:10], CSORBT
CCR
CR[0:F]
SPCR0
SPCR0
TMSK2
TMSK2
SPSR
CSPAR0
CSPAR1
CSPAR0
DDRE
DDRF
DDRGP
DDRQS
CSOR[0:10], CSORBT
CR[0:F]
SPCR1
CR[0:F]
SPCR1
TCTL2
SYNCR
SPCR2
SIMCR
RSR
PWMC
PWMC
SCSR
CFORC
CFORC
CFORC
SIMCR
SIMCR
GPTMCR
QSMCR
SPCR3
SPSR
RSR
SYPCR
SPCR3
Base Address
Autovector Enable
Bits Per Transfer
Bits Per Transfer Enable
Block Size
Bus Monitor External Enable
Bus Monitor Timing
Upper/Lower Byte Option
Carry Flag
Continue
Clock Phase
Clock Polarity
Capture/Compare Clock Output Enable
Timer Prescaler/PCLK Select Field
Completed Queue Pointer
Chip-Select [6:1]
Chip-Select [4:0]
Boot ROM Chip Select
Port E Data Direction
Port F Data Direction
Port GP Data Direction
Port QS Data Direction
Data Strobe Acknowledge
PCS to SCK Delay
Delay Before SCK
Delay After Transfer
Length of Delay After Transfer
Input Capture Edge Control
ECLK Divide Rate
Ending Queue Pointer
External Clock Off
External Reset
Force Logic Level One on PWMA
Force Logic Level One on PWMB
Framing Error
Force Output Compare
Force PWMA Value
Force PWMB Value
Freeze Bus Monitor Enable
Freeze Software Enable
Freeze Response
Freeze1
Halt
Halt Acknowledge Flag
Halt Monitor Reset
Halt Monitor Enable
HALTA and MODF Interrupt Enable