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MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
USER’S MANUAL
A-9
A
39
BG Width Negated
tGH
2—
tcyc
39A
BG Width Asserted
tGA
1—
tcyc
46
R/W Width Asserted (Write or Read)
tRWA
150
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
tRWAS
90
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
tAIST
5—
ns
47B
Asynchronous Input Hold Time
tAIHT
15
—
ns
48
DSACK[1:0] Asserted to BERR, HALT Asserted11
tDABA
—30
ns
53
Data Out Hold from Clock High
tDOCH
0—
ns
54
Clock High to Data Out High Impedance
tCHDH
—28
ns
55
R/W Asserted to Data Bus Impedance Change
tRADC
40
—
ns
56
RESET Pulse Width (Reset Instruction)
tHRPW
512
—
tcyc
57
BERR Negated to HALT Negated (Rerun)
tBNHN
0—
ns
70
Clock Low to Data Bus Driven (Show)
tSCLDD
029
ns
71
Data Setup Time to Clock Low (Show)
tSCLDS
15
—
ns
72
Data Hold from Clock Low (Show)
tSCLDH
10
—
ns
73
BKPT Input Setup Time
tBKST
15
—
ns
74
BKPT Input Hold Time
tBKHT
10
—
ns
75
Mode Select Setup Time
tMSS
20
—
tcyc
76
Mode Select Hold Time
tMSH
0—
ns
77
RESET Assertion Time12
tRSTA
4—
tcyc
78
RESET Rise Time13
tRSTR
—10
tcyc
Table A-6a 20.97 MHz AC Timing
(VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit
F1
Frequency of Operation (32.768 kHz crystal)2
f
0.13
20.97
MHz
1
Clock Period
tcyc
47.7
—
ns
1A
ECLK Period
tEcyc
381
—
ns
1B
External Clock Input Period3
tXcyc
47.7
—
ns
2, 3
Clock Pulse Width
tCW
18.8
—
ns
2A, 3A ECLK Pulse Width
tECW
183
—
ns
2B, 3B External Clock Input High/Low Time3
tXCHL
23.8
—
ns
4, 5
Clock Rise and Fall Time
tCrf
—5
ns
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
trf
—8
ns
4B, 5B External Clock Rise and Fall Time4
tXCrf
—5
ns
6
Clock High to Address, FC, SIZE, RMC Valid
tCHAV
023
ns
7
Clock High to Address, Data, FC, SIZE, RMC High Impedance
tCHAZx
047
ns
8
Clock High to Address, FC, SIZE, RMC Invalid
tCHAZn
0—
ns
9
Clock Low to AS, DS, CS Asserted
tCLSA
023
ns
9A
AS to DS or CS Asserted (Read)5
tSTSA
–10
10
ns
9C
Clock Low to IFETCH, IPIPE Asserted
tCLIA
222
ns
11
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
tAVSA
10
—
ns
12
Clock Low to AS, DS, CS Negated
tCLSN
223
ns
12A
Clock Low to IFETCH, IPIPE Negated
tCLIN
222
ns
13
AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold)
tSNAI
10
—
ns
Table A-6 16.78 MHz AC Timing, (Continued)
(VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
Symbol
Min
Max
Unit