MC68331
USER’S MANUAL
OVERVIEW
MOTOROLA
3-13
3
Figure 3-6 Separate Supervisor and User Space Map
331 S/U SEP MAP
INTERNAL REGISTERS
$000000
$FFFFFF
$FF0000
SUPERVISOR
SPACE
$7FF000
INTERNAL REGISTERS
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
$XX03FC
$XX0000
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0040–005C
006C
0064
0068
006C
0070
0074
0078
007C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
VECTOR
OFFSET
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
VECTOR
NUMBER
TYPE OF
EXCEPTION
INTERNAL REGISTERS
INTERNAL REGISTERS
USER
SPACE
$000000
$7FF000
4
$FF0000
4
$FFFFFF
$YFF000
$YFF93F
GPT
$YFFA00
RESIM
$YFFAFF
$YFFA7F
$YFFA80
RESERVED
$YFFC00
$YFFFFF
QSM
$YFF900
$YFFDFF