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參數(shù)資料
| 型號(hào)： | MC68307FG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 137/264頁(yè) |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307FG16 |
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Applications Information
10-14
MC68307 USER’S MANUAL
MOTOROLA
10.3.6 Transfer Blocks
The master M-bus controls of the number of data bytes within each transmit/receive block.
Observe Figure 10-4 and Figure 10-6, which give a summary of the activity on the M-bus
during the master transmit and master receive blocks respectively.
When the master is transmitting data (master transmit block) the slave acknowledges all
bytes received, and the master decides when the transfer is completed by setting a STOP
condition (see Figure 10-4). When the master is receiving data (master receive block) it
decides when the transfer is complete by stopping acknowledges on the last received byte,
thereby stopping the slave transmitting, and setting a STOP condition (see Figure 10-6).
10.3.7 Software Implementation
The software used is shown in Section 10.3.7.1 Software Listing 1—M-bus Master Soft-
ware and Section 10.3.7.2 Software Listing 2—M-bus Slave Software. Only the method
of enabling the M-bus and interrupts at the start of the software listings is specific to the
MC68307. Thereafter, the code is generic for any MC68300 device with an M-bus module.
The MC68300 M-bus slave software should always be set running before the master soft-
ware, such that the prospective slave is initialized as a receiver before the master transmits
the slave address.
The software uses interrupts to control the byte transfers within each block. The M-bus mas-
ter starts the transfer by transmitting the slave address. Thereafter interrupts are generated
on both the master and slave M-bus to control the test. The M-bus hardware protocol does
not care which order the interrupts are serviced by the master (transmitter or receiver) or
slave (transmitter or receiver) at the end of each byte. Consider that the master is in charge
of generating the SCL clocks to shift data out the transmitter and into the receiver, when a
transmit/receive is initiated by writing/reading the M-bus data register respectively. How-
ever, the clocks do not start until the slave has released the clock line on the bus by making
its corresponding read/write of its M-bus data register. Therefore, both MC68300 M-bus
master and slave interrupts have to initiate the next data transfer.
The slave frequency can be programmed as greater or less than that of the master. M-bus
implements a clock synchronization mechanism such that the clock with the shortest high
time and longest low time dictates the open drain clock. For example, if the programmed
slave M-bus clock frequency is less than the master, the slave can stretch the clock as nec-
essary.
The number of transfer and receive blocks and the number of data bytes within each block
can be altered in the master software. The slave software remains the same throughout. If
the user desires detailed crosschecks on the software flow, interrupt counts (for number of
bytes transferred) or a flag passing mechanisms could be implemented. For simplicity this
is not used in the example software.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
| MC68307V | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
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| MC68322AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Printer Processor |
| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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