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參數(shù)資料
| 型號： | MC68307CFG16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 259/264頁 |
| 文件大小： | 949K |
| 代理商： | MC68307CFG16 |
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EC000 Core Processor
4-18
MC68307 USER’S MANUAL
MOTOROLA
rent program counter and the copy of the status register are saved on the supervisor stack.
The saved value of the program counter is the address of the next instruction. Instruction
execution commences at the address contained in the trace exception vector.
4.6.9 Bus Error
When a bus error exception occurs, the current bus cycle is aborted. The current processor
activity, whether instruction or exception processing, is terminated, and the processor imme-
diately begins exception processing.
Exception processing for a bus error follows the usual sequence of steps. The status register
is copied, the supervisor mode is entered, and tracing is turned off. The vector number is
generated to refer to the bus error vector. Since the processor is fetching the instruction or
an operand when the error occurs, the context of the processor is more detailed. To save
more of this context, additional information is saved on the supervisor stack. The program
counter and the copy of the status register are saved. The value saved for the program
counter is advanced 2–10 bytes beyond the address of the first word of the instruction that
made the reference causing the bus error. If the bus error occurred during the fetch of the
next instruction, the saved program counter has a value in the vicinity of the current instruc-
tion, even if the current instruction is a branch, a jump, or a return instruction. In addition to
the usual information, the processor saves its internal copy of the first word of the instruction
being processed and the address being accessed by the aborted bus cycle. Specific infor-
mation about the access is also saved: type of access (read or write), processor activity (pro-
cessing an instruction), and function code outputs when the bus error occurred. The
processor is processing an instruction if it is in the normal state or processing a group 2
exception; the processor is not processing an instruction if it is processing a group 0 or a
group 1 exception. Figure 4-7 illustrates how this information is organized on the supervisor
stack. If a bus error occurs during the last step of exception processing, while either reading
the exception vector or fetching the instruction, the value of the program counter is the
address of the exception vector. Although this information is not generally sufficient to effect
full recovery from the bus error, it does allow software diagnosis. Finally, the processor com-
mences instruction processing at the address in the vector. It is the responsibility of the error
handler routine to clean up the stack and determine where to continue execution.
If a bus error occurs during the exception processing for a bus error, an address error, or a
reset, the processor halts and all processing ceases. This halt simplifies the detection of a
catastrophic system failure, since the processor removes itself from the system to protect
memory contents from erroneous accesses. Only an external reset operation can restart a
halted processor.
4.6.10 Address Error
An address error exception occurs when the processor attempts to access a word or long-
word operand or an instruction at an odd address. An address error is similar to an internally
generated bus error. The bus cycle is aborted, and the processor ceases current processing
and begins exception processing. The exception processing sequence is the same as that
for a bus error, including the information to be stacked, except that the vector number refers
to the address error vector. Likewise, if an address error occurs during the exception pro-
cessing for a bus error, address error, or reset, the processor is halted.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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