MOTOROLA
M68040 USER’S MANUAL
xxi
LIST OF ILLUSTRATIONS (Continued)
Figure
Page
Number
Title
Number
B-10
Snoop Hit Timing.......................................................................................... B-19
B-11
Snoop Miss Timing....................................................................................... B-20
B-12
Other Signal Timing ..................................................................................... B-21
C-1
MC68040V and MC68EC040V Functional Signal Groups ........................... C-3
C-2
MC68040V and MC68EC040V Initial Power-On Reset Timing ................... C-8
C-3
MC68040V and MC68EC040V Normal Reset Timing.................................. C-9
C-4
MC68040V and MC68EC040V Test Logic Block Diagram .......................... C-11
C-5
Bypass Register ........................................................................................... C-13
C-6
Output Latch Cell (O.Latch) ......................................................................... C-14
C-7
Input Pin Cell (I.Pin) .....................................................................................C-14
C-8
Output Control Cells (IO.Ctl) ........................................................................ C-15
C-9
General Arrangement of Bidirectional Pins .................................................. C-15
C-10
Circuit Disabling IEEE Standard 1149.1A ................................................... C-17
C-11
Drive Levels and Test Points for AC Specifications ..................................... C-18
C-12
Clock Input Timing Diagram .........................................................................C-21
C-13
Read/Write Timing........................................................................................ C-24
C-14
Bus Arbitration Timing .................................................................................. C-25
C-15
Snoop Hit Timing.......................................................................................... C-26
C-16
Snoop Miss Timing....................................................................................... C-27
C-17
Other Signal Timing ..................................................................................... C-28
C-18
Going into LPSTOP with Arbitration ............................................................. C-29
C-19
LPSTOP no Arbitration, CPU is Master ....................................................... C-30
C-20
Exiting LPSTOP with Interrupt...................................................................... C-31
C-21
Exiting of LPSTOP with RESET ................................................................... C-31
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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