- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4032 > MC68040FE40A (Freescale Semiconductor)IC MICROPROCESSOR 32BIT 184-CQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC68040FE40A |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 315/442闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MICROPROCESSOR 32BIT 184-CQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 绯诲垪锛� | M680x0 |
| 铏曠悊鍣ㄩ鍨嬶細 | M680x0 32-浣� |
| 閫熷害锛� | 40MHz |
| 闆诲锛� | 5V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 184-BCQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 184-CQFP锛�31.3x31.3锛� |
| 鍖呰锛� | 鎵樼洡 |
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B-6
M68040 USER鈥橲 MANUAL
MOTOROLA
MC68EC040 REV2.3 (01/31/2000)
U1, U0鈥擴ser Page Attributes
These two bits drive on the user page attribute signals (UPA1 and UPA0). If an external
bus transfer results from the access, U0 and U1 are echoed to the UPA0 and UPA1
signals, respectively. The user can program these bits to support extended addressing,
bus snooping, or other applications. The MC68EC040 does not interpret these bits.
CM鈥擟ache Mode
This field selects the cache mode and access serialization for a page as follows:
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
Detailed information on caching modes is available in Section 4 Instruction and Data
Caches, and information on serialization is available in Section 7 Bus Operation.
W鈥擶rite Protect
This bit indicates if the transparent block is write protected. If set, write and read-modi-
fy-write accesses are aborted as if the R-bit in a table descriptor were clear. Refer to 3.2.2
Descriptors for a description of table descriptors.
0 = Read and write accesses permitted.
1 = Write accesses not permitted.
B.3.2 Address Comparison
The following description of address comparison assumes that the ACRs are enabled.
Clearing the E-bit in each ACR independently disables access control, causing the proces-
sor to ignore it.
When an ACU receives a physical address, the privilege mode and the eight high-order bits
of the address are compared to the block of addresses dened by the two ACRs for the cor-
responding ACU. Each block of address space for an ACR contains an S-eld, a BASE
ADDRESS eld, and an ADDRESS MASK eld. The S-eld allows for matching either user
or supervisor accesses (or both). Setting a bit in the ADDRESS MASK eld causes the cor-
responding bit of the ADDRESS BASE to be ignored in the address comparison and privi-
lege mode. Setting successively higher order bits in the ADDRESS MASK eld increases
the size of the block of address space.
The address for the current bus cycle and an ACR address match when the privilege mode
and address bits for each (not including the masked bits) are equal. Each ACR species
write protection for the block of address space. Enabling write protection for a block of
address space causes the abortion of write or read-modify-write accesses to the block, and
an access error exception occurs.
By appropriately conguring an ACR, exible mappings can be specied. For example, to
control access to the user address space, the S-eld equals $0, and the ADDRESS MASK
eld equals $FF in all four ACRs. To control access to the supervisor address space
($00000000鈥�$0FFFFFFF) with write protection, the BASE ADDRESS eld = $0X, the
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鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鍙冩暩(sh霉)鎻忚堪 |
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| MC68040FE40V | 鍔熻兘鎻忚堪:IC MICROPROCESSOR 32BIT 184-CQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - 寰檿鐞嗗櫒 绯诲垪:M680x0 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:MPC85xx 铏曠悊鍣ㄩ鍨�:32-浣� MPC85xx PowerQUICC III 鐗归粸(di菐n):- 閫熷害:1.2GHz 闆诲:1.1V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:783-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:783-FCPBGA锛�29x29锛� 鍖呰:鎵樼洡 |
| MC68040RC25 | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
| MC68040RC25A | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE MMU FPU RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68040RC25V | 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU 32B W/ CACHE MMU RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324 |
| MC68040RC33 | 鍒堕€犲晢:MOTOROLA 鍒堕€犲晢鍏ㄧū:Motorola, Inc 鍔熻兘鎻忚堪:M68000-compatible, high-performance, 32-bit microprocessors |
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