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參數(shù)資料
| 型號(hào)： | MC68020FE25E |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 232/306頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MICROPROCESSOR 32BIT 132CQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 25MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BCQFP |
| 供應(yīng)商設(shè)備封裝： | 132-CQFP（24x24） |
| 包裝： | 托盤(pán) |
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2- 2
M68020 USER’S MANUAL
MOTOROLA
2.1 PRIVILEGE LEVELS
The processor operates at one of two privilege levels: the user level or the supervisor
level. The supervisor level has higher privileges than the user level. Not all processor or
coprocessor instructions are permitted to execute at the lower privileged user level, but all
are available at the supervisor level. This arrangement allows a separation of supervisor
and user so the supervisor can protect system resources from uncontrolled access. The
S-bit in the SR is used to select either the user or supervisor privilege level and either the
USP or an SSP for stack operations. The processor identifies a bus access (supervisor or
user mode) via the function codes so that differentiation between supervisor level and
user level can be maintained.
In many systems, the majority of programs execute at the user level. User programs can
access only their own code and data areas and can be restricted from accessing other
information. The operating system typically executes at the supervisor privilege level. It
has access to all resources, performs the overhead tasks for the user-level programs, and
coordinates user-level program activities.
2.1.1 Supervisor Privilege Level
The supervisor level is the higher privilege level. The privilege level is determined by the
S-bit of the SR; if the S-bit is set, the supervisor privilege level applies, and all instructions
are executable. The bus cycles for instructions executed at the supervisor level are
normally classified as supervisor references, and the values of the FC2–FC0 signals refer
to supervisor address spaces.
In a multitasking operating system, it is more efficient to have a supervisor stack space
associated with each user task and a separate stack space for interrupt-associated tasks.
The MC68020/EC020 provides two supervisor stacks, master and interrupt; the M bit of
the SR selects which of the two is active. When the M-bit is set, references to the SSP
implicitly or to address register seven (A7) explicitly, access the MSP. The operating
system sets the MSP for each task to point to a task-related area of supervisor data
space. This arrangement separates task-related supervisor activity from asynchronous,
I/O-related supervisor tasks that may be only coincidental to the currently executing task.
The MSP can separately maintain task control information for each currently executing
user task, and the software updates the MSP when a task switch is performed, providing
an efficient means for transferring task-related stack items. The other supervisor stack
pointer, the ISP, can be used for interrupt control information and workspace area as
interrupt handling routines require.
When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor
privilege level, and operation is the same as supervisor mode in the MC68000,
MC68HC001, MC68008, and MC68010. (The processor is in this mode after a reset
operation.) All SSP references access the ISP in this mode.
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