
7-6
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
Table 7-7. Single Operand Instruction
Execution Times
Instruction
CLR
Size
Byte
Word
Long
Byte
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
Register
8
(2/0)
8
(2/0)
10
(2/0)
10
(2/0)
8
(2/0)
8
(2/0)
10
(2/0)
8
(2/0)
8
(2/0)
10
(2/0)
8
(2/0)
8
(2/0)
10
(2/0)
8
(2/0)
10
(2/0)
8
(2/0)
8
(2/0)
8
(2/0)
8
(2/0)
Memory
12
(2/1)+
16
(2/2)+
24
(2/4)+
12
(2/1)+
12
(2/1)+
16
(2/2)+
24
(2/4)+
12
(2/1)+
16
(2/2)+
24
(2/4)+
12
(2/1)+
16
(2/2)+
24
(2/4)+
12
(2/1)+
12
(2/1)+
14
(2/1)+
8
(2/0)+
8
(2/0)+
8
(2/0)+
NBCD
NEG
NEGX
NOT
Scc
Byte, False
Byte, True
Byte
Byte
Word
Long
TAS
TST
+Add effective address calculation time.
7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES
Table 7-8 lists the timing data for the shift and rotate instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-8. Shift/Rotate Instruction Execution Times
Instruction
ASR, ASL
Size
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
Byte
Word
Long
Register
10+2n
(2/0)
10+2n
(2/0)
12+n2
(2/0)
10+2n
(2/0)
10+2n
(2/0)
12+n2
(2/0)
10+2n
(2/0)
10+2n
(2/0)
12+n2
(2/0)
10+2n
(2/0)
10+2n
(2/0)
12+n2
(2/0)
Memory
—
16
(2/2)+
—
—
16
(2/2)+
—
—
16
(2/2)+
—
—
16
(2/2)+
—
LSR, LSL
ROR, ROL
ROXR, ROXL
+Add effective address calculation time for word operands.
n is the shift count.