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參數(shù)資料
| 型號： | MC56U512NACA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MultiMediaCard Specification |
| 中文描述： | 多媒體卡規(guī)格 |
| 文件頁數(shù)： | 64/66頁 |
| 文件大?。?/td> | 1422K |
| 代理商： | MC56U512NACA |
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MultiMediaCard
TM
64
Figure 4-20 Timing diagram: Read CSD register
Single Block Write
The host may deselect a card (by raising the CS) at any time during the card busy period (refer to the
given timing diagram). The card will release the DataOut line one clock after the CS going high. To check
if the card is still busy it needs to be reselected by asserting (set to low) the CS signal. The card will
resume busy signal (pulling DataOut low) one clock cycle after the falling edge of CS.
Figure 4-20 Timing Diagram: Single Block Write
Multiple Block Write
The timimg behaviour of the multiple block write transaction starting from the comamnd up to the first
data block is identical to the single block write. Figure 63 describes the timing between the data blocks of
a multiple block write transaction. Timing of the ‘Stop Tran’ token is identical to a standard data block.
After the “Stop Tran” token is received ny the card, the data on the DataOut line is undefined for one byte
(NBR), after which a Busy token may apear. The host may deselect and reselect the card during every
busy period between the data blocks. Timing for toggling the CS signal is identical to the Single block
write transaction.
Figure 4-21 Timing Diagram: Multiple Block Write
Timing Values
Min
NCS
0
NCR
1
NCX
0
Max
8
8
8
(10/8)*(TAAC*Fo
p+100*NSAC)
8
8
8
Unit
8Clock cycles
8Clock cycles
8Clock cycles
NAC
1
8Clock cycles
NRC
NWR
NEC
1
1
0
8Clock cycles
8Clock cycles
8Clock cycles
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