參數(shù)資料
型號： MC56F8256VLF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù)： 62/88頁
文件大?。?/td> 4050K
代理商： MC56F8256VLF
Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
65
7.20
Freescale’s Scalable Controller Area Network (MSCAN)
Figure 26. Bus Wake-up Detection
7.21
Inter-Integrated Circuit Interface (I2C) Timing
Table 36. MSCAN Timing
Characteristic
Symbol
Min
Max
Unit
Baud Rate
BRCAN
—
1
Mbps
Bus Wake-up detection
TWAKEUP
TIPBUS
—
μs
Table 37. I2C Timing
Characteristic
Symbol
Standard Mode
Unit
Minimum
Maximum
SCL Clock Frequency
fSCL
0
100
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHD; STA
4.0
—
μs
LOW period of the SCL clock
tLOW
4.7
—
μs
HIGH period of the SCL clock
tHIGH
4.0
—
μs
Set-up time for a repeated START condition
tSU; STA
4.7
—
μs
Data hold time for I2C bus devices
tHD; DAT
01
1 The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.452
2 The maximum t
HD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
μs
Data set-up time
tSU; DAT
2503
3 A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT > = 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I
2C bus specification) before the SCL line is released.
—ns
Rise time of SDA and SCL signals
tr
—
1000
ns
Fall time of SDA and SCL signals
tf
—
300
ns
Set-up time for STOP condition
tSU; STO
4.0
—
μs
Bus free time between STOP and START condition
tBUF
4.7
—
μs
Pulse width of spikes that must be suppressed by the input filter
tSP
N/A
ns
TWAKEUP
MSCAN_RX
CAN receive
data pin
(Input)
相關(guān)PDF資料
PDF描述
MC56F8245VLD 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP44
MC56F8245MLD 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP44
MC56F8322MFAE 0-BIT, 120 MHz, OTHER DSP, PQFP48
MC56F8322VFAE 0-BIT, 120 MHz, OTHER DSP, PQFP48
MC56F8347VPY60 16-BIT, 120 MHz, OTHER DSP, PQFP160
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8257 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Battery chargers and management
MC56F8257MLH 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSC 64 LQFP 64K FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8257VLH 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSC 64 LQFP 64K FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F825X 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Battery chargers and management
MC56F82723VFM 制造商:Freescale Semiconductor 功能描述:MC56F Series 100 MHz 32 KB Flash 3 KB SRAM 32-Bit Microcontroller - QFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*