參數(shù)資料
型號(hào): MC56F8246MLF
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 67/88頁(yè)
文件大小: 0K
描述: DSC 48K FLASH 60MHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 48KB(24K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 管件
Overview
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor
7
— Maximum slave module frequency = module clock frequency/2
— 13-bit baud rate divider for low speed communication
Two inter-integrated circuit (I2C) ports
— Operation at up to 100 kbps
— Support for master and slave operation
— Support for 10-bit address mode and broadcasting mode
— Support for SMBus, Version 2
One Freescale Scalable Controller Area Network (MSCAN) module
— Fully compliant with CAN protocol Version 2.0 A/B
— Support for standard and extended data frames
— Support for data rate up to 1 Mbit/s
— Five receive buffers and three transmit buffers
Computer operating properly (COP) watchdog timer capable of selecting different clock sources
— Programmable prescaler and timeout period
— Programmable wait, stop, and partial powerdown mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of clock sources from four sources in support of EN60730 and IEC61508:
– On-chip relaxation oscillator
– External crystal oscillator/external clock source
– System clock (IP bus to 60 MHz)
Power supervisor (PS)
— On-chip linear regulator for digital and analog circuitry to lower cost and reduce noise
— Integrated low voltage detection to generate warning interrupt if VDD is below low voltage detection (LVI)
threshold
— Integrated power-on reset (POR)
– Reliable reset process during power-on procedure
– POR is released after VDD passes low voltage detection (LVI) threshold
— Integrated brown-out reset
— Run, wait, and stop modes
Phase lock loop (PLL) providing a high-speed clock to the core and peripherals
— 2x system clock provided to Quad Timers and SCIs
— Loss of lock interrupt
— Loss of reference clock interrupt
Clock sources
— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for
normal operation
— External clock: crystal oscillator, ceramic resonator, and external clock source
Cyclic Redundancy Check (CRC) Generator
— Hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
— High-speed hardware CRC calculation
— Optional feature to transpose input data and CRC result via transpose register, required on applications where
bytes are in LSb (Least Significant bit) format.
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