參數(shù)資料
型號: MC56F8156VFVE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: ROHS COMPLIANT, LQFP-144
文件頁數(shù): 23/178頁
文件大小: 910K
代理商: MC56F8156VFVE
Register Descriptions
56F8356 Technical Data, Rev. 13
Freescale Semiconductor
119
Preliminary
device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Table 6-2 Control of Pads Using SIM_GPS Control 1
Pin Function
Control Registers
Comments
GPIOC_PER
GPIOC_DTR
SIM
_
GPS
Qu
ad
T
imer
SC
R
Re
gister
OEN
b
its
GPIO Input
0
GPIO Output
0
1
Quad Timer Input /
Quad Decoder Input 2
1
0
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.
Quad Timer Output /
Quad Decoder Input 3
1—
0
1
GPIOC_PER Register
GPIO Controlled
I/O Pad Control
SIM_ GPS Register
Quad Timer Controlled
SPI Controlled
0
1
0
1
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