參數(shù)資料
型號: MC56F8155VFG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Hybrid Controllers
中文描述: 16位混合控制器
文件頁數(shù): 107/164頁
文件大小: 2086K
代理商: MC56F8155VFG
Register Descriptions
56F8355 Technical Data, Rev. 5.0
Freescale Semiconductor
Preliminary
107
6.5.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$601D.
Least Significant Half of JTAG ID (SIM_LSH_ID)
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
Figure 6-8
) corresponds to a functional group of pins. See
Table 2-2
to identify which pins can deactivate the internal pull-up resistor.
SIM Pull-up Disable Register (SIM_PUDR)
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bit 15
6.5.6.2
This bit controls the pull-up resistors on the FAULTA3 pin.
PWMA1—Bit 14
6.5.6.3
This bit controls the pull-up resistors on the CAN_RX pin.
CAN—Bit 13
6.5.6.4
This bit controls the pull-up resistors on the EMI_MODE pin
EMI_MODE—Bit 12
Note:
In this package, this input pin is double-bonded with the adjacent V
SS
pin and this bit should be
changed to a 1 in order to reduce power consumption.
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
Write
RESET
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
PWMB
PWMA0
0
CTRL
0
JTAG
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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相關代理商/技術參數(shù)
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