參數(shù)資料
型號: MC56F8014VFAE
廠商: Freescale Semiconductor
文件頁數(shù): 5/124頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTRLR 32-LQFP
標準包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-LQFP
包裝: 托盤
配用: DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
56F8014 Technical Data, Rev. 11
102
Freescale Semiconductor
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All the address and data buses described here are internal.
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz
(used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
4T
ns
Minimum GPIO pin Assertion for Interrupt
tIW
2T
ns
RESET deassertion to First Address Fetch3
3. During Power-On Reset, it is possible to use the 56F8014 internal reset stretching circuitry to extend this period to 2^21T.
tRDA
96TOSC + 64T
97TOSC + 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
tIF
—6T
ns
GPIO pin
(Input)
TIW
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