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| 型號(hào)： | MC56F8014MFAE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 114/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL SIGNAL CTLR 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 16KB（8K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤 |
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Architecture Block Diagram
56F8014 Technical Data, Rev. 11
Freescale Semiconductor
9
create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8014’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1 illustrates
how the 56800E system buses communicate with internal memories and the IPBus Bridge, as well as
showing the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals
and control blocks connected to the IPBus Bridge. Figure 1-3 details how the device’s I/O pins are muxed.
The figures do not show the on-board regulator and power and ground signals. They also do not show the
multiplexing between peripherals or the dedicated GPIOs. Please see Part 2 Signal/Connection
Descriptions to see which signals are multiplexed with those of other peripherals.
1.5 Synchronize ADC with PWM
ADC conversion can be synchronized with the PWM module via Quad Timer channel 2 and 3 if needed.
Internally, the PWM synch signal — which is generated at every PWM reload —can be connected to the
timer channel 3 input, and the timer channel 2 and channel 3 outputs are connected to the ADC sync inputs.
Timer channel 3 output is connected to SYNC0 and timer channel 2 is connected to SYNC1. The setting
is controlled by the TC3_INP bit in the SIM Control Register; see Section 6.3.1.
SYNC0 is the master ADC sync input, used to trigger both ADCA and ADCB in sequence and parallel
mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger
ADCA. See MC56F8000RM, the 56F801X Peripheral Reference Manual, for additional information.
1.6 Multiple Frequency PWM Output
When both PWM channels of a complementary pair in software control mode and software control bits
are set to 1, each complementary PWM signal pair — PWM 0 and 1; PWM 2 and 3; and PWM 4 and 5 —
can select a PWM source from one of the following sources. This will enable each PWM pair and PWM2
to output PWM signals at different frequencies.
External GPIO input:
— GPIOB2 input can be used to drive PWM 0 and 1
— GPIOB3 input can be used to drive PWM 2
— GPIOB4 input can be used to drive PWM 4 and 5
Quad Timer output:
— Timer0 output can be used to drive PWM 0 and 1
— Timer2 output can be used to drive PWM 2
— Timer3 output can be used to drive PWM 4 and 5
ADC conversion result:
— Signal of over/under limit of ADC sample 0 can be used to drive PWM 0 and 1
— Signal of over/under limit of ADC sample 1 can be used to drive PWM 2
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC56F8014VFAE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC BAHAMAS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8023 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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| MC56F8025 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8025E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Product Brief |
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