
56F8014 Features
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
5
Part 1 Overview
1.1.1
Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection
On-chip memory, including a low-cost, high-volume Flash solution
— 16KB of Program Flash
— 4KB of Unified Data/Program RAM
EEPROM emulation capability
1.1.3
Peripheral Circuits for 56F8014
One Pulse Width Modulator (PWM) module with five PWM outputs and three Fault inputs; fault-tolerant
design with dead time insertion; supports both center-aligned and edge-aligned modes
One eight-input, 12-bit, Analog-to-Digital Converter (ADC), which support two simultaneous conversions
with dual, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer Channels
2 and 3
One 16-bit Quad Timer module (TMR) totaling four pins: Timer works in conjunction with the PWM and
ADC
One Serial Communication Interface (SCI) with LIN Slave functionality
One Serial Peripheral Interface (SPI)
Computer Operating Properly (COP)/Watchdog timer