- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26800 > MC54HC74AJ (ON SEMICONDUCTOR) HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC54HC74AJ |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | MC54HC74AJ |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
Dual D Flip-Flop with Set
and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC74A is identical in pinout to the LS74. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two D flip–flops with individual Set, Reset, and
Clock inputs. Information at a D–input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip–flop. The Set and Reset inputs are
asynchronous.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q2
PIN 14 = VCC
PIN 7 = GND
MC54/74HC74A
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Outputs
Set Reset Clock Data
Q
L
H
X
H
L
H
L
X
L
H
L
X
H*
H
L
H
L
H
L
X
No Change
H
X
No Change
H
X
No Change
* Both outputs will remain high as long as
Set and Reset are low, but the output
states are unpredictable if Set and Reset
go high simultaneously.
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
VCC
Q2
GND
Q1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
1
14
1
14
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC54HCT157AJ | HCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDIP16 |
| MC7400P | 74 SERIES, QUAD 2-INPUT NAND GATE, PDIP14 |
| MC7400L | 74 SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
| MC7401P | 74 SERIES, QUAD 2-INPUT NAND GATE, PDIP14 |
| MC741VHC157DR2 | AHC/VHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC54HC75J | 制造商:Motorola Inc 功能描述: |
| MC54HC86AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input Exclusive OR Gate |
| MC54HC86J | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input Exclusive OR Gate |
| MC54HCT00A | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input NAND Gate with LSTTL-Compatible Inputs |
| MC54HCT00AJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad 2-Input NAND Gate with LSTTL-Compatible Inputs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。