- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371038 > MC54HC354J (MOTOROLA INC) 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs PDF資料下載
參數(shù)資料
| 型號(hào)： | MC54HC354J |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| 中文描述： | HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 206K |
| 代理商： | MC54HC354J |
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1995
10/95
"! ! !
"!# ! !
!
!!"!"!
High–Performance Silicon–Gate CMOS
The MC54/74HC354 is identical in pinout to the LS354. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC354 selects one of eight latched binary Data Inputs, as deter-
mined by the Address Inputs. The information at the Data Inputs is stored
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is
held high. The Address information may be stored in the transparent
Address Latch, which is enabled by the active–high Address–Enable pin.
The device outputs are placed in high–impedance states when Output
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.
The HC354 has a clocked Data Latch that is not transparent.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 326 FETs or 81.5 Equivalent Gates
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
8
7
6
5
4
3
2
1
8–BIT
DATA
LATCH
(TRANS–
PARENT)
8–BIT
MULTI–
PLEXER
DATA
INPUTS
3–STATE
OUTPUT
CONTROL
Y
Y
19
18
3–STATE
DATA
OUTPUTS
DATA–LATCH
ENABLE
9
A0
A1
A2
14
13
12
ADDRESS
INPUTS
ADDRESS–LATCH
ENABLE
11
OE1
OE2
OE3
15
16
17
OUTPUT
ENABLES
ADDRESS
LATCH
(TRANS–
PARENT)
PIN 20 = VCC
PIN 10 = GND
20
1
19
2
18
3
17
4
VCC
D7
16
5
15
6
14
7
13
8
12
9
11
10
Y
D6
Y
D5
OE3
D4
OE2
D3
OE1
D2
A0
D1
A1
D0
A2
Data–Latch
Enable
Address–Latch
Enable
GND
Pinout: 20–Lead Package
(Top View)
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HC354DW | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| MC74HC354 | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| MC74HC354N | 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs |
| MC54HC374AJ | Octal 3-State Noninverting D Flip-Flop |
| MC54HC374 | Octal 3-State Noninverting D Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC54HC365 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Hex 3-State Noninverting Buffer with Common Enables |
| MC54HC365J | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Hex 3-State Noninverting Buffer with Common Enables |
| MC54HC366 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Hex 3-State Inverting Buffer with Common Enables |
| MC54HC366J | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Hex 3-State Inverting Buffer with Common Enables |
| MC54HC367 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。