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參數(shù)資料
| 型號： | MC44BC374EJBR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR ANT BOOSTER 24TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 調(diào)制器 |
| 應用： | 機頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
High-Speed I2C Compatible Bus
MC44BC373/374 Technical Data
13.3 Levels Definition
Figure 12. SDA Levels
13.4 High-Speed I2C Compatible Bus Format
Figure 13. SCL and SDA Bus Timing
13.5 I2C Write Mode Format and Bus Receiver
The bus receiver operates the I2C compatible data format. The chip address (I2C bus) is:
In write mode, each ninth data bit (bits 9, 18, 27, 36, and 45) is an acknowledge bit (ACK) during which
the MCU sends a logic 1 and the Modulator circuit answers on the data line by pulling it low. Besides the
chip address, the circuit needs two or four data bytes for operation. The following data byte sequences are
the permitted incoming information:
After the chip address, two or four data bytes may be received.
If three (3) data bytes are received, the third one is ignored.
If five (5) or more data bytes are received, the fifth and following ones are ignored, and the last ACK
pulse is sent at the end of the fourth data byte.
1 1 0 01010 (ACK)=$CA( hex) in write mode
Example 1
STA
CA
C1
C0
STO
Example 2
STA
CA
FM
FL
STO
Example 3
STA
CA
C1
C0
FM
FL
STO
Example 4
STA
CA
FM
FL
C1
C0
STO
With:
STA = Start condition
CA = Chip Address
FM = Frequency information, high order bits
FL = Frequency information, low order bits
C1 = Control information, high order bits
CO = Control information, low order bits
STO = Stop condition
SDA
...
0V
Vcc
Vih
Vil
dead band
1
2
3
4
5
6
7
8
9 10
14
11 12 13
45
44
15
19
16 17 18
STA
Chip Address ($CA)
ACK
First Data Byte (C1 or FM)
Data
ACK
Stop
SCL
SDA
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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