參數(shù)資料
型號: MC44605
廠商: ON SEMICONDUCTOR
英文描述: High Safety, Latched Mode, GreenLine PWM Controller for (Multi)Synchronized Applications
中文描述: 高安全性,鎖存模式,二七二三六七六七的PWM控制器(同步多應(yīng)用)
文件頁數(shù): 15/20頁
文件大?。?/td> 328K
代理商: MC44605
MC44605
http://onsemi.com
15
Figure 12. Overcurrent in a WSCD Case
(VCS + Vshift)/RS
time
P
VCS/RS
(Vin x t/Lleak
Vin x t/Lp
t
t
Now, in normal working, this overcurrent Ipk is equal to:
Ipk
Vin
δ
t
LP
where: Vin is the input voltage (rectified a.c. line)
While in a WSCD case:
( Ipk)WSCD
Vin
LLeak
δ
t
Consequently, as the leakage inductor value is generally
much lower than the primary one (less than 5% generally),
the overcurrent is much higher in the WSCD case. That is
why this fault can be detected by detecting the high
overcurrents.
So, the WSCD block consists of comparing the sensed
current to a reference equal to: (Vcs + Vshift), where Vshift is
a voltage proportional to the current injected in the pin 15
(refer to Figure 13).
Figure 13. WSCD
Vin
R
Isense
Vcs
Disabling
Block
3.75
Vshift shift = 500
CWSCD
VWSCD
Pin 7
Pin 15
Vshift
Ishift
MC44605
Now, as the overcurrent level depends on the input voltage
Vin, it is preferable to use a Vshift proportional to this input
voltage instead of a constant Vshift. So, the WSCD pin must
be connected to Vin through a resistor that fixes Vshift by
adjusting the current injected in this pin 15.
Finally, when there is a winding short circuit, an
overcurrent is detected by the WSCD comparator. The
output of this comparator, VWSCD, is connected to the
disabling block (refer to the disabling block §).
Maximum Power Limitation Section (MPL)
The MPL block is designed to calculate this input power
using the following equation:
Pin
1
2
LP
Ipk2
f
where: Lp is the inductor value
Ipk is the inductor peak current
f is the switching frequency
As Vcs is proportional to the inductor peak current
(Vcs = Rs x Ipk), the squared Ipk value is estimated by
building a current source proportional to Vcs2. This current
is chopped by a calibrated pulse Sf, generated at each new
oscillator cycle (refer to Figure 14).
Finally, using an external resistor and capacitor network
(RMPL, CMPL) on the MPL pin, a voltage VMPL,
proportional to the input power can be obtained.
In effect,
VMPL
RMPL
kMPL
Vcs2
(Sf)
T
where: kMPL is the multiplier gain
(Sf) is the width of the calibrated pulse
T is the switching (oscillator) period
Now, as Sf is built comparing the oscillator to a constant
level, (Sf) is proportional to Rref and CT:
(Sf)
k1
Rref
CT
where: k1 is a constant
On the other hand, kMPL that is depending on the reference
current source Iref, is proportional to 1/Rref:
kMPL
k2
1
Rref
where: k2 is a constant
So:
VMPL
RMPL
k1
k2
Vcs2
f
CT
where: CT is the oscillator capacitor
Finally:
VMPL
RMPL
Γ
MPL
Vcs2
f
CT
where:
Γ
MPL is the MPL parameter as defined in the
specification. This is a constant equal to the product
(k1 x k2).
Now, as:
Pin
1
2
LP
Ipk2
f
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