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參數(shù)資料
| 型號(hào)： | MC44460 |
| 廠商： | Motorola, Inc. |
| 英文描述： | PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 中文描述： | 子母畫(huà)中畫(huà)（PIP）控制器 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 439K |
| 代理商： | MC44460 |
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MC44460
12
MOTOROLA ANALOG IC DEVICE DATA
CIRCUIT DESCRIPTION
The MC44460 Picture–in–Picture (PIP) controller is
composed of an analog section, logic section and an
8.0 k x 8–bit DRAM array. A block diagram showing details of
all of these sections is shown in the Representative Block
Diagram.
The analog section includes an Input Switch, Sync
Processor, Filters, PLLs, NTSC Decoder, ADC, DACs, NTSC
Encoder and Output Switch. All necessary controls are
provided by registers in the logic section. These registers are
set by external control through the I2C Bus.
In operation, the MC44460 overlays a single PIP on the
main video in either a 1/9th or 1/16th size. In 1/9th, the PIP is
152 samples (114 Y, 19 V, 19 U) by 70 lines and occupies
8094 bytes of the 8192 byte DRAM. The 1/16 size is 112
samples (84 Y, 14 V, 14 U) by 52 lines and occupies 4452
bytes of the DRAM. An extra line of data is stored for each
PIP size to allow for interlace disorder correction. The 6:1:1
samples are formatted by the logic section as follows in order
to efficiently utilize memory:
Byte 1: Y0(5:0), V(1:0)
Byte 2: Y1(5:0), V(3:2)
Byte 3: Y2(5:0), V(5:4)
Byte 4: Y3(5:0), U(1:0)
Byte 5: Y4(5:0), U(3:2)
Byte 6: Y5(5:0), U(5:4)
Refer to the block diagram. Both the video inputs are
applied to an input switch which is controlled by the I2C bus
interface. Either of the inputs is applied to the PIP processing
circuitry and either to the main video signal path of the output
switch. The signal applied to the PIP processor also provides
the vertical sync reference to the PIP processor.
The PIP output from the switch is applied to a 1.0 MHz
cutoff low pass GmC biquad filter to extract the luminance
signal and a similar bandpass filter to pass chroma to the
decoder section. These filters are tracked to a master GmC
cell using subcarrier as a reference. A single–ended
transconductance stage with relatively large signal handling
ability (>2.5 Vpp @ 4.5 V VCC) is used to avoid potential
noise problems.
Figure 2. NTSC Decoder
Color
Killer
In
90
°
ACC
Switching
PLL
Filter
XVCO/
Divide
Mult 1
Mult 2
BG
H
U
V
0
°
The NTSC Decoder (Figure 2) consists of two multipliers,
a voltage controlled 4 X S/C crystal oscillator/divider,
Automatic Color Control (ACC) block, Color Kill circuit and
necessary switching. During Burst Gate time, the ACC block
in the NTSC Decoder is calibrated with respect to burst
magnitude by applying the output of multiplier 1 to the
reference input of the ACC block. The result is U and V
outputs which are 0.6 V
±
0.5 dB for burst amplitudes varying
from –12 dB to 3.0 dB. The second multiplier serves as a
phase detector during color burst to match the 90 degree
output from the XVCO to the 180 degree color burst and feed
a correction current to the PLL filter. The phase is correct
when the two signals are 90 degrees out of phase.
During the H drive time, the output of the multipliers is fed
to the YUV clamp, filtered to 200 KHz and input along with the
Y signal to the multiplexer.
The YUV samples are fed through a multiplexer to a single
six bit A/D converter. The A/D is a flash type architecture and
is capable of digitizing at a 20 MHz sample rate. It is
comprised of an internal bandgap source voltage reference,
a 64 tap resistor ladder comparator array, a binary encoder
and output latches. Once the multiplexer has switched,
sufficient time is provided to allow the A/D converter to settle
before the reading is latched. The encoder code is
determined from the values of any comparators which are not
metastable.
The multiplexer and A/D converter receive and convert the
YUV data at a 4FSC/3 rate for a 1/9th size picture or FSC for
a 1/16th size picture. The samples are taken in the following
way to simplify the control logic:
Y,V,Y,U,Y,V,Y,U
To provide a 6:1:1 format, one of three U and V samples is
saved to memory giving a luminance sample rate of 2FSC/3
for a 1/9th picture and FSC/2 for a 1/16 picture. In the vertical
direction, one line of every 3 (1/9th picture) or 4 (1/16th
picture) are saved. In order to avoid objectionable artifacts, a
piece–wise vertical filter is used to take a weighted average
on the luminance samples. For three lines (1/9th size) the
weight is 1/4 + 1/2 + 1/4 and for four lines (1/16 size) it is
1/4 + 1/4 + 1/4 + 1/4. This filter also delays the luma samples
correcting for the longer chroma signal path through the
decoder.
Finally the logic incorporates a field generator to
determine the current field in order to correct interlace
disorders arising from a single field memory.
A separate process runs in the logic section to create the
PIP window on the main picture. Control signals are
generated and sent to the memory controller to read data
from the field memory. Data from the eight bit memory are
then de–multiplexed into a six bit YUV format, borders are
added, blanking is generated for the video clamps and sent to
the Y, U and V DACs. Since the PIP display is based on a
data clock, it is important to minimize the main display clock
skew on a line by line basis. Skew is minimized in the
MC44460 by reclocking the display timebase to the nearest
rising or falling edge of a 16FSC clock. This produces a
maximum line to line skew of approximately 8.0 ns which is
not perceptible to the viewer. The PIP write logic also
incorporates a field generator for use by the memory
controller for interlace disorder correction. Interlace disorder
can occur when the line order of the two fields of the PIP
image is swapped due to a mismatch with the main picture
field or due to an incomplete field being displayed from
memory. The main and PIP field generators, along with
monitoring, when the PIP read address passes the PIP write
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| MC44461 | PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462B | Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462 | Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44463B | RV Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 09V; Power: 2W; High Isolation 2W Converter; Approved for Medical Applications; EN and UL Safety Certificates; 6kVDC Isolation; Skinny DIP24 Package; Optional Continuous Short Circuit Protected; Fully Encapsulated; Very Low Isolation Capacitance |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC44460B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44461 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44461B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
| MC44462B | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Y-C PICTURE-IN-PICTURE (PIP) CONTROLLER |
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