
Chapter 19 96 Kbyte Flash Module (S12FTS96KV1)
Freescale Semiconductor
MC9S12Q128
551
Rev 1.10
19.4.1.2
Command Write Sequence
The Flash command controller is used to supervise the command write sequence to execute program,
erase, and erase verify algorithms.
Before starting a command write sequence, the ACCERR and PVIOL ags in the FSTAT register must be
clear and the CBEIF ag should be tested to determine the state of the address, data, and command buffers.
If the CBEIF ag is set, indicating the buffers are empty, a new command write sequence can be started.
If the CBEIF ag is clear, indicating the buffers are not available, a new command write sequence will
overwrite the contents of the address, data, and command buffers.
A command write sequence consists of three steps which must be strictly adhered to with writes to the
Flash module not permitted between the steps. However, Flash register and array reads are allowed during
a command write sequence. The basic command write sequence is as follows:
1. Write to a valid address in the Flash array memory.
2. Write a valid command to the FCMD register.
3. Clear the CBEIF ag in the FSTAT register by writing a 1 to CBEIF to launch the command.
The address written in step 1 will be stored in the FADDR registers and the data will be stored in the
FDATA registers. When the CBEIF ag is cleared in step 3, the CCIF ag is cleared by the Flash command
controller indicating that the command was successfully launched. For all command write sequences, the
CBEIF ag will set after the CCIF ag is cleared indicating that the address, data, and command buffers
are ready for a new command write sequence to begin. A buffered command will wait for the active
operation to be completed before being launched. Once a command is launched, the completion of the
command operation is indicated by the setting of the CCIF ag in the FSTAT register. The CCIF ag will
set upon completion of all active and buffered commands.