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| 型號： | MC3510 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | ECONOLINE：RSZ / P - 1kVDC 2kVDC隔離UL94V - 0封裝材料所需的散熱片，無外置。組件所需的環(huán)形磁ContinuousShort電路保護(hù)（/ P的后綴） |
| 文件頁數(shù)： | 26/75頁 |
| 文件大?。?/td> | 1023K |
| 代理商： | MC3510 |
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MC3510 Technical Specifications
26
5.2
CP chip pin description table
Pin Name and number Direction
~WriteEnbl
1
R/~W
4
Description
When
low
, this signal enables data to be written to the bus.
This signal is
high
when the CP chip is performing a read, and
low
when it is
performing a write.
This signal is
low
when the data and address are valid during CP
communications.
This signal is
low
when peripheral devices on the data bus are being addressed.
This signal is
low
when external memory is being accessed.
This is the master reset signal. When brought
low
, this pin resets the processor to
its initial conditions.
This signal is the inverse of
R/~W
; it is
high
when
R/~W
is low, and vice versa. For
some decode circuits, this is more convenient than
R/~W
.
This pin receives serial data from the asynchronous serial port. If serial
communication is not used, this pin should be tied to V
cc
.
This pin transmits serial data to the asynchronous serial port.
This pin sets the serial port enable line. SrlEnable is always
high
for the point-to-
point protocol and is
high
during transmission for the multi-drop protocol.
When
low
, this signal causes an interrupt to be sent to the host processor.
This signal interrupts the CP chip when a host I/O transfer is complete. It
should be connected to
CPIntrpt
of the parallel interface chip.
If the parallel interface is disabled (see below) this signal can be left unconnected
or tied to V
cc
.
This signal enables/disables the parallel communication with the host. If this
signal is tied
high
, the parallel interface is enabled. If this signal is tied
low
the
parallel interface is disabled. See section 6 of this manual for more information
on parallel communication.
output
output
~Strobe
6
output
~PeriphSlct
~RAMSlct
~Reset
130
129
41
output
output
input
W/~R
132
output
SrlRcv
43
input
SrlXmt
SrlEnable
44
99
output
output
~HostIntrpt
I/OIntrpt
98
53
output
input
PrlEnable
65
input
WARNING! This signal should only be tied high if an external
logic device that implements the parallel communication logic
included in the design. This signal is an output during device reset
and as such any connection to GND or V
cc
must be via a series
resistor.
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
Data12
Data13
Data14
Data15
9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28
bi-directional
Multi-purpose data lines. These pins comprise the CP chip’s external data bus,
used for all communications with peripheral devices such as external memory or
DACs. They may also be used for parallel-word input and for user-defined I/O
operations.
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