參數(shù)資料
型號: MC33884DWR2
廠商: MOTOROLA INC
元件分類: 其它接口
英文描述: SWITCH MONITOR INTERFACE
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO24
封裝: SOIC-24
文件頁數(shù): 10/21頁
文件大小: 235K
代理商: MC33884DWR2
10
MOTOROLA TSG IC DEVICE DATA
PIN FUNCTIONAL DESCRIPTION
CSB Pin
The system MCU selects the MC33884 to be
communicated with through the use of the CSB pin. With the
CSB in a logic low state, command words may be sent to the
MC33884 via SI and switch status can be received by the
MCU via SO. Falling edge of CSB enables the SO output,
latches the state of the INTB pin, operating mode and the state
of the external switch inputs. Rising edge of CSB disables the
SO driver, resets the INTB pin to logic [1], activates the
received command word, and allows the MC33884 to act upon
new data obtained from switch inputs. To avoid any spurious
data, it is essential that the high–to–low and low–to–high
transition of the CSB signal occur only when SCLK is in a logic
low state. Internal to the MC33884 is an active pull up on CSB.
SCLK Pin
The system clock pin (SCLK) clocks the internal 16–bit shift
register of the MC33884. The serial input (SI) data is latched
into the input shift register on the rising edge of SCLK signal.
The serial output pin (SO) shifts the switch status bits out on
the falling edge of SCLK. False clocking of the shift register
must be avoided to guarantee validity of data. It is essential
that the SCLK pin be in a logic low state whenever chip select
pin (CSB) makes any transition. For this reason it is
recommended, though not necessary, that the SCLK pin be
commanded to a low logic state as long as the device is not
accessed (CSB in logic high state). When the CSB is in a logic
high state, any signal on the SCLK and SI pin will be ignored
and the SO pin is Tri–Stated (high impedance).
SI Pin
This pin is used for serial instruction data input. SI
information is latched into the input register on the rising edge
of SCLK. A logic high state present at SI when SCLK rises,
programs a [1] into the command word on rising edge of the
CSB signal. To program a complete word, 16 bits of
information must be entered into the MC33884. Internal to the
IC is an active pull down on the SI pin.
SO Pin
The serial output (SO) pin is the output from the shift
register. The SO pin remains Tri–State until the CSB pin
transitions to a logic low state. All “open switches” are
reported as [0], all ‘closed switches’ are reported as [1]. The
negative transition of CSB will make status bit 15 available on
SO. Each successive negative clock will make the next status
bit available. The SI/SO shifting of the data follows a
first–in–first–out protocol with both input and output words
transferring the Most Significant Bit (MSB) first.
MASL pin
The MASL pin is required when multiple MC33884 devices
are used in one module. The MASL (Master/Slave) identifies
which device will be the master and which will be the slave.
Master/Slave identification is used during Polling mode. In the
Polling mode the Master device has it’s internal oscillator
running while the Slave device oscillator is shutdown. When
polling the Master device wakes the Slave via the SYNC pin.
This feature provides minimal quiescent from VPWR and VDD
pins.
SYNC Pin
The SYNC input is used by slave IC during Polling mode.
The SYNC allows multiple MC33884 ICs to poll the multiple
inputs at the same time. The Master controls the polling
period. The Slave is allowed to shut down it’s oscillator to
conserve current. When the Slave receives the SYNC signal
from the Master, the Slave starts the internal oscillator and
reads the switch inputs.
INTB Pin
The INTB pin is an interrupt output from the MC33884. The
INTB pin is an open drain output with an internal pull up. In
normal mode a switch state change will trigger the INTB pin.
The INTB pin and INT bit (flag) is latched on falling edge of
CSB. This permits the MCU to determine the origin of the
interrupt. The flag INT bit in the SPI word is the inverse of the
INTB pin. The INTB pin is cleared on rising edge of CSB. In
Polling mode the INTB pin is active only during the ON time
(when sink and source currents are active).
RSTB Pin
The RSTB pin is active low reset input to the MC33884.
When asserted, the MC33884 will reset all internal registers,
timers, and enter a sleep mode (with all switch inputs in a
Tri–State condition). Only an MCU SPI command word will
wake the MC33884 from a sleep state. The RSTB pin may be
controlled directly from a general purpose I/O pin or from a
system/MCU reset.
VBG Pin
The VBG pin requires a 130 k
to ground for standard
wetting and sustain currents. The device is tested with a 0.1%
value, but a standard 1.0% could be used for proper
functionality.
VPWR Pin
VPWR pin is battery/supply source pin for the MC33884.
The VPWR pin requires external reverse battery/supply and
transient protection. Maximum input voltage on VPWR is 40
volts. All wetting currents and sustain currents are derived
from VPWR.
SP1 – SP4 Pins
The MC33884 has 4 switch sense inputs that may be
programmed to read switch–to–ground or switch–to–battery/
supply contacts. Transient battery/supply voltages greater
than 40 volts must be clamped by an external device. Surface
mount 0805 MOVs and transient voltage suppressors (TVS)
are available in SOT–23 packages. The sensed input is
compared with an internal 4.0 volt reference. When
programmed to sense switch–to–battery, sensed voltages
greater than 4.0 volts are interpreted as a CLOSED switch.
Sensed voltages less than 4.0 V are interpreted as an OPEN
switch. The opposite holds true when inputs are programmed
to sense switch–to–ground. Further programming can set the
wetting currents or make the inputs Tri–State. Programming
methods are provided in the following section.
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