參數(shù)資料
型號(hào): MC33884DW
廠商: MOTOROLA INC
元件分類: 其它接口
英文描述: SWITCH MONITOR INTERFACE
中文描述: SPECIALTY INTERFACE CIRCUIT, PDSO24
封裝: SOIC-24
文件頁數(shù): 14/21頁
文件大?。?/td> 235K
代理商: MC33884DW
14
MOTOROLA TSG IC DEVICE DATA
DESCRIPTION (Continued)
WT[2:1] — Wake–Up Time
These bits let the device assert an external interrupt (INTB) at the following intervals during Polling mode (MOD2=MOD1=1).
Wake–Up Delay Prescales
WT[2:1]
Multiplier
Selected
Wake–Up Interrupt, tWAKE (ms)
[tDETECT (2.8ms typ.) * Multiplier]
2400 – 3200
00
512+1
01
256+1
1200 – 1600
10
128+1
600 – 750
11
64+1
290 – 360
CP[4:1] — Configure Programmable Switch
Configure the programmable inputs SP[4:1] to detect either an external switch–to–ground (internal current source) or an external
switch–to–battery (internal current sink). Note that this configuration may be entered in any of the three valid Operating Modes
(see MOD[2:1]) within the Run command.
Programmable Switch Bit Definition
CPx
External Switch to:
0
Ground
1
Battery
Tri–State Command
This command places an external switch into a “Tri–State” condition, essentially disconnecting the wetting current (if the switch
is metallic) and the sustain current. The internal input–threshold comparator is still internally connected to its external pin. This
command does not change the mode of operation (e.g., a Tri–State command received while in Polling mode leaves the part in
that mode). Note that the Tri–State register clears all bits to [0] (all inputs in Tri–State) in response to a hardware reset; all inputs
also remain in Tri–State after exiting the Sleep mode.
MSB
Bit
LSB
Bit
Command
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Tri–State
0
0
1
1
TG6
TG5
TG4
TG3
TG2
TG1
TP4
TP3
TP2
TP1
TB2
TB1
RESET VALUES:
Tri–State Register
0
0
0
0
0
0
0
0
0
0
0
0
TG[6:1] — Tri–State Switch–to–Ground
TB[2:1] — Tri–State Switch–to–Battery
TP[4:1] — Tri–State Programmable Switch
Tri–State Bit Definition
TGx, TBx, TPx
Input Configured to:
0
Input Disabled [DEFAULT]
1
Input Enabled
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