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參數(shù)資料
| 型號： | MC33883R2 |
| 廠商： | Motorola, Inc. |
| 英文描述： | H-Bridge Gate Driver IC |
| 中文描述： | H橋門驅(qū)動(dòng)器集成電路 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 556K |
| 代理商： | MC33883R2 |
33883
14
Go to: www.freescale.com
Protection
Gate Protection
The low-side driver is supplied from the built-in low-drop
regulator. The high-side driver is supplied from the internal
charge pump buffered at CP_OUT.
The low-side gate is protected by the internal linear
regulator, which ensures that V
GATE_LS
does not exceed the
maximum V
GS
. Especially when working with the charge pump,
the voltage at CP_OUT can be up to 65 V. The high-side gate
is clamped internally in order to avoid a V
GS
exceeding 18 V.
Gate protection does not include a flyback voltage clamp that
protects the driver and the external MOSFET from a flyback
voltage that can occur when driving inductive load. This flyback
voltage can reach high negative voltage values and needs to be
clamped externally, as shown in
Figure 10
.
Figure 10. Gate Protection and Flyback Voltage Clamp
Load Dump and Reverse Battery
V
CC
and V
CC2
can sustain load a dump pulse of 40 V and
double battery of 24 V. Protection against reverse polarity is
ensured by the external power MOSFET with the free-wheeling
diodes forming a conducting pass from ground to V
CC
.
Additional protection is not provided within the circuit. To protect
the circuit an external diode can be put on the battery line. It is
not recommended putting the diode on the ground line.
Temperature Protection
There is temperature shutdown protection per each half-
bridge. Temperature shutdown protects the circuitry against
temperature damage by switching off the output drivers. Its
typical value is 175°C with an hysteresis of 15°C.
dV/dt at V
CC
V
CC
voltage must be higher than (SRC_HS voltage minus a
diode drop voltage) to avoid perturbation of the high-side driver.
In some applications a large dV/dt at terminal C2 owing to
sudden changes at V
CC
can cause large peak currents flowing
through terminal C1, as shown in
Figure 11
.
For positive transitions at terminal C2, the absolute value of
the minimum peak current, I
C1
min, is specified at 2.0 A for a
t
C1
min duration of 600 ns.
For negative transitions at terminal C2, the maximum peak
current, I
C1
max, is specified at 2.0 A for a t
C1
max duration of
600 ns. Current sourced by terminal C1 during a large dV/dt will
result in a negative voltage at terminal C1 (
Figure 11
). The
minimum peak voltage V
C1
min is specified at -1.5 V for a
duration of t
C1
max = 600 ns. A series resistor with the charge
pump capacitor (Ccp) capacitor can be added in order to limit
the surge current.
Figure 11. Limits of C1 Current and Voltage with Large Values of dV/dt
Output
Driver
OUT
Output
Driver
OUT
IN
L
1
M
2
GATE_LS
SRC_HS
GATE_HS
Inductive
Flyback Voltage
Clamp
IN
D
cl
M
1
V
CC
CP_OUT
LR_OUT
V
GS
< 14 V
Under All
Conditions
t
C1
max
t
C1
min
V
CC
I
(C1+C2)
I
C1
max
I
C1
min
V
(LR_OUT)
0 V
V
(C1)
0 A
V
C1
min
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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