參數(shù)資料
型號: MC33567D-2
廠商: ON SEMICONDUCTOR
元件分類: 模擬信號調理
英文描述: Dual Linear Controller for High Current Voltage Regulation
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: SOIC-8
文件頁數(shù): 4/12頁
文件大?。?/td> 88K
代理商: MC33567D-2
MC33567
http://onsemi.com
4
OPERATING DESCRIPTION
Introduction
The MC33567 series is a family of Dual Linear FET
Controllers designed for Power Management applications
where high current, voltage regulation is needed. Some
computer applications include:
1.2 V Power Supply
1.515 V AGP (Advanced Graphic Port) and GTL+
(Gunning Transistor Logic Intel’s electrical bus
technology)
1.818 V I/O planes on motherboards
2.3 V Power Supply
2.525 V Clock and memory
The MC33567 provides tight output voltage regulation,
(Vout), and incorporates individual SHDN controls for each
FET controller and voltage protection by sensing the output
voltage.
Output:
The MC33567 provides tight output voltage regulation
from one or two supply voltages using 2 external NChannel
MOSFETs. Each controller operates independently and
regulates the output voltage to a predetermined level (1.2 V,
1.515 V 1.818 V, 2.3 V or 2.525 V). In addition, regulator 2
of the MC335671 incorporates a Vin bypass mode on which
the external FET is fully enhanced.
Shutdown:
The regulated outputs of the MC33567 can be disabled
with the use of the SHDN pin. It also determines the output
voltage level. SHDN can be controlled externally from
board signals like the AGP or GTL+ as shown in Figure 3.
Figure 3. 1.5 V/3.3 V AGP Card Detection
*Vin while on bypass mode (MC335671 only)
1
2
3
4
8
7
6
5
MC33567
DRV2
SENSE2
SHDN2
3.3 V
AGP
Card Type
Detection
AGP
Card
Voltage
Vout or Vin*
12 V (VCC)
3.3 V (Vin)
10 k
Listed below are the SHDN threshold voltage levels and
the corresponding regulator output voltages:
1. If the SHDN pin is left open, the output voltage is set
to its regulated value.
2. If a voltage less than 0.8 V is applied to the SHDN pin,
the output voltage is set to 0 V.
3. If a voltage greater than 1.3 V and less than 4.1 V is
applied to the SHDN pin, the output voltage is set to its
regulated voltage.
4. If the SHDN voltage is pulled above 4.1 V, the
MC33567 enters a Vin bypass mode. In this mode, the
MOSFET is fully enhanced and the output voltage is
the MOSFET drain voltage (Vin) minus the MOSFET
drainsource on voltage VDS(on). This feature is only
available on REGULATOR 2 of the MC335671.
Table 1 summarizes the output voltage options and its
relationship with VSHDN.
Table 1. Logic Table for SHDN Pin
Device
VSHDN (V)
Vout (V)
MC335671
REGULATOR 1
No Connect
0.8 V
1.3 V
1.818 V
0 V
1.818 V
REGULATOR 2
No Connect
0.8 V
VSHDN
4.1 V
1.3 V
4.1 V
1.515 V
0 V
1.515 V
VinVDS(on)
(BypaMode)
MC335672
REGULATOR 1 &
REGULATOR 2
No Connect
0.8 V
1.3 V
2.525 V
0 V
2.525 V
MC335673
REGULATOR 1
No Connect
0.8 V
1.3 V
2.3 V
0 V
2.3 V
REGULATOR 2
No Connect
0.8 V
1.3 V
1.2 V
0 V
1.2 V
Undervoltage Detection:
If Vout drops below 75% of the regulated threshold for
greater than 250
μ
s or a short circuit condition is present, that
output will go into short circuit or Hiccup Mode. While in
Hiccup mode, the output is turned ON for 1.0 ms and OFF
for 40 ms for a duty cycle of 1:41 as shown in Figure 4. This
mode will continue as long as the fault is present. Once the
fault is removed, the regulator will resume normal
operation.
40 ms
1 ms
Figure 4. Hiccup Mode Duty Cycle
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