參數(shù)資料
型號: MC33566
廠商: ON SEMICONDUCTOR
英文描述: Smart Voltage Regulator for Peripheral Card Applications(用于PCI/NIC卡應(yīng)用的小型低壓差穩(wěn)壓器)
中文描述: 智能穩(wěn)壓器(用于的PCI /卡應(yīng)用的周邊網(wǎng)卡卡應(yīng)用的小型低壓差穩(wěn)壓器)
文件頁數(shù): 2/6頁
文件大?。?/td> 61K
代理商: MC33566
MC33566
http://onsemi.com
2
PIN ASSIGNMENTS AND FUNCTIONS
Pin #
Pin Name
Pin Description
1
+3.3 V
aux
Auxiliary input. Typical voltage 3.3 V.
2
+5.0 V
in
This is the input supply for the IC. Typical voltage 5.0 V. (Notes 1 and 2)
3
Gnd
Logic and power ground.
4
+3.3 V
out
3.3 V output provided to the application circuit (output current is sourced to this pin from the
5.0 V input.)
5
Drive out
This output drives a Pchannel MOSFET with up to 2000 pF of “effective” gate capacitance.
Recommended devices are the MMFT5P03HD and MTSF1P02HD. Drive out has active internal
pullup and pulldown circuitry to guarantee fast transitions.
MAXIMUM RATINGS
(T
C
= 25
°
C, unless otherwise noted)
Rating
Symbol
Value
Unit
+5.0 V
in
Supply Voltage
V
in
7.0
Vdc
V
in
0.5 (Note 3)
Vdc
Operating Ambient Temperature
T
a
5.0 to +85
°
C
Operating Junction Temperature
T
J
5.0 to +150
°
C
Lead Temperature (Soldering, 10 seconds)
T
L
300
°
C
Storage Temperature
T
stg
55 to +150
°
C
Package Thermal Resistance
R
θ
JA
(Note 4)
65
°
C/W
AC ELECTRICAL SPECIFICATIONS
(Notes 5, 6, and 7)
Characteristic
Symbol
Min
Typ
Max
Unit
Drive High Delay (V
in
ramping up)
C
drive
= 1.2 nF, measured from +5.0 V
in
= V
thresHi
to V
Drive
= 2.0 V
t
DH
0.5
3.5
μ
S
Drive Low Delay (V
in
ramping down)
C
drive
= 1.2 nF, measured from +5.0 V
in
= V
thresLo
to V
Drive
= 2.0 V
t
DL
0.5
3.5
μ
S
1. See 5.0 V Detect Thresholds Diagram.
2. Recommended source impedance for 5.0 V supply:
0.12 . This will ensure that I
o
x R
source
< V
hyst
, thus avoiding driveout toggling during
5.0 V detect threshold transitions.
3. V
in
should not be allowed to go negative relative to ground.
4. Mounted on recommended minimum PCB pad on FR4, 2oz. copper circuit board.
5. AC specs are guaranteed by characterization, but not production tested after characterization.
6. See Figure 3. Application Block Diagram.
7. See Timing Diagram.
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