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參數(shù)資料
| 型號： | MC33565D |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Single Output LDO, 400mA, Fixed(3.0V), Low Noise, Fast Transient Response 5-SOT-23 -40 to 85 |
| 中文描述： | 3.3 V FIXED POSITIVE LDO REGULATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 88K |
| 代理商： | MC33565D |
MC33565
4
MOTOROLA ANALOG IC DEVICE DATA
Vref
Compensation
&
Hysteresis
+5 Vin
Ref &
Detect
5V detect
Comp
Driver
Drive out
+3.3 Vout
Sense in
+3.3 Vin
Hyst sw
External
P–channel
MOSFET
+3.3 Vout
External
4.7
μ
F
cap
LDO
Figure 1. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Input Blocking
– The internal NPN pass transistor of the
LDO regulator ensures that no significant reverse current will
flow from +3.3 Vout back to the +5 Vin input when the 5V input
is not powered and the 3.3 Vin supply is present.
5 Volt Detect
– Internal circuitry detects the presence of
the 5V input supply. When the 5V supply drops below a given
threshold, the +3.3 Vin bypass transistor (an external
P–channel MOSFET) is enabled. The 5V detect logic is
active throughout the entire range of ramp–up from 0 to 5.5V.
Additionally, the Drive out signal is never turned ON or OFF
inappropriately during ramp–up of the +5 Vin supply. Also,
+3.3 Vout never drops below 3.0V while +5 Vin is above the
5V detect minimum threshold.
Glitch–free Transfer
– The design of the 5V detect
circuitry and Drive out control circuitry guarantees that the
+3.3 Vout will not exceed the output voltage specification
listed in the table of DC Operating Specifications even with
+5 Vin ramping up and down at the extremes of the slew rates
in the table of AC Operating Specifications (provided the
device is used with an MGSF1P02ELT PMOS FET on Drive
out along with a minimum 4.7
μ
F capacitor on the +3.3 Vout).
Offset Voltage Performance
– To ensure performance
when external offsets are present on the +5 Vin and +3.3 Vin
power inputs, the device has been designed to be capable of
operating with either one or both of these inputs rising from or
falling to zero volts, or with offsets of 0.05V to 0.9V as the
inputs ramp up and down.
Motherboard/
Mainboard
PCI Slot
Figure 2. Application Block Diagram
+5 Vin
N/C
+3.3 Vin
Gnd
Drive out
+3.3 Vout
Sense in
N/C
1
2
3
4
8
7
6
5
MC33565
PCI NIC/Card
Circuitry
5V
3.3V aux
4.7
μ
F
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC33565DG | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep And Active Mode RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| MC33565DMR2 | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| MC33565DMR2G | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep And Active Mode RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| MC33565DR2 | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| MC33565DR2G | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 200mA w/Sleep And Active Mode RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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