參數(shù)資料
型號: MC33560DW
廠商: ON SEMICONDUCTOR
元件分類: 模擬信號調(diào)理
英文描述: Single Output LDO, 400mA, Fixed(3.0V), Low Noise, Fast Transient Response 8-MSOP -40 to 85
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: PLASTIC, SO-24
文件頁數(shù): 15/24頁
文件大?。?/td> 435K
代理商: MC33560DW
MC33560
http://onsemi.com
15
3V/5V programming:
It is possible to set the card supply
voltage to 3V or 5V at any time, before DC/DC converter
start, or during converter operation. When switching from
3V to 5V, a 160ms (typical) delay blanks the undervoltage
fault detection to allow filter capacitor charging.
PWM:
The free–running integrated oscillator has two
working modes:
variable on–state and fixed frequency (typically
120KHz) for average to heavy loads.
variable on–state and variable frequency for light loads.
The frequency can be as low as a few kHz if no load is
connected to
CRDVCC
.
The charging current of the timing capacitor is related to
the VBAT
supply voltage, to allow better line regulation, and
to increase stability.
Filtering Capacitor:
A high value allows efficient
filtering of card current spikes. Low values allow low
start–up charging current. Care must be taken not to
combine low capacitor value with high current limiting, as
this can generate high ripple. Usual values range from 4.7
μ
F
to 47
μ
F, depending on current limiting.
Selecting the external components L1 and RLIM:
The
choice of inductor L1 and resistor R4 is made by using figure
8 (5V card) and/or figure 9 (3V card) on page 8:
First, determine the maximum current that the application
requires to supply to the card (ICCmax, on the y–axis)
Then, select one curve that crosses the selected ICCmax
level. The curve is associated with an inductance value
(22
μ
H, 47
μ
H, or 100
μ
H).
Finally, use the intersection of the curve and the ICCmax
level to find the Rlim value on the x–axis.
Good starting values are : L1
=47
μ
H; Rlim
=0.5
Note also that, for a high inductance value (100
μ
H), the
filtering capacitor is generally charged before inductance
current reaches current limitation, while for alow inductance
value, the current limitation is activated after a few converter
cycles.
Battery requirements:
Having determined the L1
and
Rlim
values, the maximum current drawn from the battery
supply is shown by the curves in figures 6 and 7.
When the application is powered by a single 3V battery,
special care has to be taken to extend its lifetime. When
lithium batteries approach the end–of–life, their internal
resistance increases, while voltage decreases. This
phenomenon can prevent the start–up of the DC/DC
converter if the current limiting is set too high, because of the
filtering capacitor charging current.
CLOCK GENERATOR
The primary purpose of the clock generator module is to
match the smartcard operating frequency to the system
frequency. The source frequency can be provided to
ASYCLKIN
by the microcontroller itself or from an
external oscillator circuit.
In programming mode
(
RDYMOD=L
and
CS
asserted
low) the three input variables
PWRON
,
IO
and
RESET
are
used to configure the two output variables
CRDVCC
and
CRDCLK
as described in table 3. This circuit setup is
latched during the positive transition of
CS
.
Furthermore, in asynchronous mode the system clock
frequency
ASYCLKIN
can be divided by a factor of 1, 2 or
4. The circuit controls the frequency commutation to
guarantee that the card clock signal remains free from spikes
and glitches. In addition, this circuit ensures that
CRDCLK
signal pulses will not be shorter than the shortest and/or
longer than the longest of the clock signals present before
and after programming changes .
The
INVOUT
output is provided to drive other circuits
without additional load to the microprocessor quartz
oscillator. It can also be used to build a local RC oscillator.
This driver has been optimized for low consumption; it has
no hysteresis, and input levels are not symmetrical. If the
ASYCLKIN
pin is connected to a sine wave, the duty cycle
will not always be 50% at
INVOUT
.
Clock generator operating principles
Synchronous Clock:
This clock is used mainly for
memory cards. It can also be used for asynchronous
(microprocessor) cards, allowing the use of two different
clock sources. The status of
SYNCLK
is latched at
CRDCLK
when
CS
goes high, so that data (the
IO
pin) and clock are
always consistent at the card connector, whatever the
CS
status is. When using the synchronous clock, the clock
output becomes active only when the MC33560 is selected
with
CS
.
Asynchronous Clock:
This clock is used mainly for
microprocessor cards. When applied, the clock output
remains active even when the MC33560 is not selected with
CS
, in order to keep the microprocessor running and avoid
an unwanted reset. The
ASYCLKIN
signal is buffered at the
INVOUT
pin, so that several MC33560 systems can use the
same clock with one load only.
Depending on programming, the frequency is fed directly,
or divided by 2 or by 4 to the
CRDCLK
pin. If the duty cycle
of the applied clock signal is not exactly symmetrical, it is
recommended that the clock signal be divided by two or four
to guarantee 50% duty cycle.
Clock Signal Synchronization and Consistency
(see
figure 29). The clock divider includes synchronization logic
that controls the switch from synchronous clock to
asynchronous (and vice–versa), from any division ratio to
any other ratio, during
CS
changes and at power up. The
synchronization logic guarantees that each clock cycle on
the
CRDCLK
pin is finished before changing clock
selection (and has always the adequate duration), regardless
of the moment the programming is changed.
At power–up, when
ASYCLKIN
is selected, the clock
signal at the
CRDCLK
pin has an entire length, according
to the selected divide ratio, whatever the
ASYCLKIN
signal
is versus the internal sequencer timing.
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