參數(shù)資料
型號(hào): MC33493DTB
廠商: MOTOROLA INC
元件分類: 消費(fèi)家電
英文描述: PLL tuned UHF Transmitter for Data Transfer Applications
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO14
封裝: TSSOP-14
文件頁數(shù): 3/20頁
文件大?。?/td> 595K
代理商: MC33493DTB
RF OUTPUT STAGE
MOTOROLA
MC33493 Technical Data
3
Table 1: Band selection and associated divider ratios
BAND Input
Level
Band (MHz)
315
434
Low
868
An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the
RF output stage is disabled.
RF OUTPUT STAGE
The output stage is a single ended square wave switched current source. Harmonics are present in the output
current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical
application demonstrates compliance to ETSI standard.
A resistor R
ext
connected to the REXT pin controls the output power allowing a trade-off between radiated power
and current consumption.
The output voltage is internally clamped to V
cc
±
2V
be
(typ. V
cc
±
1.5V @ T
A
=25
°
C).
MODULATION
A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation
is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output
stage state:
DATA=0
output stage off,
DATA=1
output stage on.
If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This
modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the
external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel.
The logic level applied on pin DATA controls the state of this internal switch:
DATA=0
switch off,
DATA=1
switch on.
DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty
cycle cannot exceed
±
1 reference period (
±
75ns for a 13.56MHz crystal).
This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation
multiplied by the PLL Divider Ratio (see table 1).
Frequency
PLL Divider
Ratio
Crystal Oscillator
Frequency (MHz)
9.84
High
32
13.56
64
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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