參數(shù)資料
型號(hào): MC33389CDH
廠商: MOTOROLA INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: System Basis Chip with Low Speed Fault Tolerant CAN
中文描述: DATACOM, INTERFACE CIRCUIT, PDSO20
封裝: POWER, HSOP-20
文件頁(yè)數(shù): 29/35頁(yè)
文件大?。?/td> 609K
代理商: MC33389CDH
MC33389
MOTOROLA
29
MC33389
Freescale Semiconductor, Inc.
The next two registers (IMR1 and IMR2) are used to mask the interrupt function.
Table 54. IMR2 — Interrupt Mask Control Register 2
To enable the appropriate interrupt, the mask bit has to be set to 1. For disabling the interrupt the bit must be cleared to 0.
After a power on reset or RSTB = low, the bits are cleared to 0. All interrupts are disabled. Explanation for the abbreviations:
HV : V
bat
high voltage
HT : High temperature on V1 or V2
MTPW : Medium temperature pre-warning on V1 or V2
BATU: Battery undervoltage (BatFail)
BUSF : CAN bus failure
SPIE : SPI error
WU : Wake-up
Table 55. ISR1 — Interrupt Source Register
The next two registers (ISR1 and ISR2) are used to read the interrupt source.
Table 56. ISR2 — Interrupt Source Register 2
All bits in registers ISR1 and ISR2 are copies of the appropriate bits in different SPI registers. For a faster read out, these bits
are merged in ISR1 and ISR2. A reset cannot be done for registers ISR1 and ISR2.
Table 57. TCR—Transceiver Control/Status Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IMR1
$01D
R
HV
HTPW
MTPW
BATU
W
RESET
0
0
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IMR2
$01E
R
BUSF
SPIE
WU
W
RESET
0
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
$021
R
HV
HTPW
MTPW
BATU
W
RESET
0
0
0
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ISR
$022
R
BUSF
SPIE
WU
W
RESET
0
0
0
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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