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  • 參數(shù)資料
    型號: MC33368P
    廠商: ON SEMICONDUCTOR
    元件分類: 穩(wěn)壓器
    英文描述: 50mA Switched-Cap DC/DC Converter 8-MSOP
    中文描述: 0.01 A POWER FACTOR CONTROLLER, PDIP16
    封裝: PLASTIC, DIP-16
    文件頁數(shù): 9/20頁
    文件大?。?/td> 476K
    代理商: MC33368P
    MC33368
    http://onsemi.com
    9
    at very low duty cycles, preventing their destruction. If the
    short circuit fault is removed, the power supply system will
    turn on by itself in a normal startup mode after the restart
    delay has timed out.
    Output Switching Frequency Clamp
    In normal operation, the MC33368 operates the boost
    inductor in the critical mode. That is, the inductor current
    ramps to a peak value, ramps down to zero, then
    immediately begins ramping positive again. The peak
    current is programmed by the multiplier output within the
    IC. As the input voltage haversine declines to near zero, the
    output switch on–time becomes constant, rather than going
    to zero because of the small integrated dc voltage at Pin 5
    caused by C2, R3 and R5. Because of this, the average line
    current does not exactly follow the line voltage near the zero
    crossings. The Output Switching Frequency Clamp
    remedies this situation to improve power factor and
    minimize EMI generated in this operating region. The
    values of R10 and C7, as shown in Figure 15, program a
    minimum off–time in the frequency clamp which overrides
    the zero current detect signal, forcing a minimum off–time.
    This allows discontinuous conduction operation of the boost
    inductor in the zero crossing region, and the average line
    current more nearly follows the voltage. The Output
    Switching Frequency Clamp function can be disabled by
    connecting the FC input, Pin 13, to the VCC supply Pin 12.
    For best results, the minimum off–time, determined by the
    values of R10 and C7, should be chosen so that ts(min) = t(on)
    + t(off)fc. Output drive is inhibited when the voltage at the
    frequency clamp input is less than 2.0 V. When the output
    drive is high, C7 is discharged through an internal 100
    μ
    A
    current source. When the output drive switches low, C7 is
    charged through R10. The drive output is inhibited until the
    voltage across C7 reaches 2.0 V, establishing a minimum
    off–time where:
    t(off)fc
    R10 C7 loge
    1
    2
    VCC
    Output
    The IC contains a CMOS output driver that was
    specifically designed for direct drive of power MOSFETs.
    The Gate Output is capable of up to
    ±
    1500 mA peak current
    with a typical rise and fall time of 50 ns with a 1.0 nF load.
    Additional internal circuitry has been added to keep the Gate
    Output in a sinking mode whenever the Undervoltage
    Lockout is active. This characteristic eliminates the need for
    an external gate pull–down resistor. The totem–pole output
    has been optimized to minimize cross–conduction current
    during high speed operation.
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