參數(shù)資料
型號: MC33291DWR2
廠商: MOTOROLA INC
元件分類: 外設(shè)及接口
英文描述: Eight Output Switch with Serial Peripheral Interface I/O
中文描述: SIPO BASED PRPHL DRVR, PDSO24
封裝: PLASTIC, SOP-24
文件頁數(shù): 10/24頁
文件大小: 633K
代理商: MC33291DWR2
33291
10
Go to: www.freescale.com
Electrical Performance Curves
Figure 3. Valid Data Delay Time and
Valid Time Test Circuit
Figure 4. Enable and Disable Time Test Circuit
Figure 5. Valid Data Delay Time and
Valid Time Waveforms
Figure 6. Enable and Disable Time Waveforms
V
DD
= 5.0 V
SCLK
SO
C
L
= 200 pF
33291
Under
Test
C
L
represents the total capacitance of the test fixture and probe.
CS
SO
C
L
= 20 pF
33291
Under
Test
V
DD
= 5.0 V
V
Pull-Up
= 2.5 V
R
L
= 1.0 k
C
L
represents the total capacitance of the test fixture and probe.
SCLK
SO
(Low-to-High)
SO
(High-to-Low)
t
valid
t
dly(lh)
t
dly(hl)
0.2 V
DD
0.7 V
DD
t
r (SO)
t
f (SO)
0.7 V
DD
0.2 V
DD
0.7 V
DD
50%
0.2 V
DD
0
t
r (SI)
< 50 ns
< 50 ns
t
f (SI)
5.0 V
V
0H
V
0L
V
0H
V
0L
SO (Low-to-High) is for an output with internal conditions such that the
low-to-high transition of CS causes the SO output to switch from high
to low.
90%
10%
10%
10%
90%
90%
CS
SO
(High-to-Low)
SO
(Low-to-High)
0.2 V
DD
0.7 V
DD
< 50 ns
< 50 ns
t
r(SI)
t
f(SI)
t
SO(en)
t
SO(dis)
t
SO(en)
t
SO(dis)
V
Tri-State
5.0 V
0
t
SO(dis)
V
Tri-State
V
0H
1. SO (high-to-low) waveform is for SO output with internal conditions such that
SO output is low except when an output is disabled as a result of detecting a
circuit fault with CS in a High Logic state, e.g. open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such that
SO output is high except when an output is disabled as a result of detecting a
circuit fault with CS in a High Logic state, e.g. shortened load.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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