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參數(shù)資料
| 型號(hào)： | MC33289 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual High-Side Switch |
| 中文描述： | 雙高邊開(kāi)關(guān) |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大小： | 345K |
| 代理商： | MC33289 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33289
3
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1, 2
5, 6
15, 16
19, 20
V
BAT
Voltage Supply (Battery)
These are the power supply pins of the device. These pins are directly connected with
the lead frame of the package and are tied to the drain of the switching MOSFET. These
pins can be directly connected to the battery voltage. In addition to their supply function,
these pins participate to the thermal behavior of the device in conducting the heat from
the switching MOSFET to the printed circuit board.
3, 4
OUT1
Output Channel 1
These pins are the output one terminals. They connect directly to the source of the
power MOSFET. These pins are used by the control circuitry to sense the device output
voltage. The R
DS(ON)
is 40 m
maximum per output at 25
°
C and will increase to a
maximum of 75 m
at 150
°
C junction temperature.
7, 14
NC
No Connect
These pins do not connect.
8
IN1
Input Channel 1
These are the device input pins. They control their associated outputs. The levels are
CMOS compatible. When the input is a logic low, the associated output MOSFET is in
the OFF state. When input is high, the MOSFET is turned ON and the load is activated.
When both inputs are low, the device is in Standby mode and its supply current is
reduced. Each input pin has an internal active pull-down, so it will not float if
disconnected.
9
ST1
Status Channel 1
These pins are the channel one fault detection flags. Their internal structure is an open
drain architecture with an internal clamp at 6.0 V. An external pull-up resistor connected
to V
DD
(5.0 V) is required. This is an active low output. If the device is in its normal
condition the status lines will be high. If open load or other fault occurs, the associated
channel status flag will be pulled low. Please see Functional Truth Table.
10
OLDE
Open Load Detection
Enable
This pin is a digital input, enabling the open load current diagnostic circuitry. When
OLDE is a logic low, the open load circuitry is not powered and the bias current draw of
the device is at a minimum. If OLDE is a logic high, the open load circuitry is functional
at the price of a higher bias current draw. OLDE pin has a pull down resistor.
11
GND
Ground
Ground of the integrated circuit.
12
ST2
Status Channel 2
These pins are the channel two fault detection flags. Their internal structure is an open
drain architecture with an internal clamp at 6V. An external pull up resistor connected to
Vdd (5.0 V) is needed. This is an active low output. If the device is in its normal condition
the status lines will be high. If open load or other fault occurs, the associated channel
status flag will be pulled low. Please, see Functional Truth Table,
Table 1
.
13
IN2
Input Channel 2
These are the device input pins. They control their associated outputs. The levels are
CMOS compatible. When the input is a logic low, the associated output MOSFET is in
the OFF state. When input is high, the MOSFET is turned ON and the load is activated.
When both inputs are low, the device is in Standby mode and its supply current is
reduced. Each input pin has an internal active pull down, so it will not float if
disconnected.
17, 18
OUT2
Output Channel 2
These pins are the output two terminals. They are connected to the source of the power
MOSFET. These pins are used by the control circuitry to sense the device output
voltage. The R
DS(ON)
is 40 m
maximum per output at 25
°
C and will increase to a
maximum of 75 m
at 150
°
C junction temperature.
V
BAT
V
BAT
OUT1
OUT1
V
BAT
V
BAT
NC
IN1
ST1
OLDE
V
BAT
V
BAT
OUT2
OUT2
V
BAT
V
BAT
NC
IN2
ST2
GND
4
5
6
7
8
9
10
2
3
20
18
17
14
13
12
11
16
15
19
1
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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