參數資料
型號: MC312XDP512J1CALR
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP112
封裝: 20 X 20 MM, LEAD FREE, LQFP-112
文件頁數: 840/1350頁
文件大小: 7418K
代理商: MC312XDP512J1CALR
Chapter 12 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
539
12.4.7.4
Reset
The reset values of registers and signals are described in Section 12.3, “Memory Map and Register
Denition”, which details the registers and their bit elds.
If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit
garbage, or the byte last received from the master before the reset.
Reading from the SPIDR after reset will always read a byte of zeros.
12.4.7.5
Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is
a description of how the SPI makes a request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
The interrupt ags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
12.4.7.5.1
MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be congured for the
MODF feature (see Table 12-2). After MODF is set, the current transfer is aborted and the following bit is
changed:
MSTR = 0, The master bit in SPICR1 resets.
The MODF interrupt is reected in the status register MODF ag. Clearing the ag will also clear the
interrupt. This interrupt will stay active while the MODF ag is set. MODF has an automatic clearing
12.4.7.5.2
SPIF
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does
not clear until it is serviced. SPIF has an automatic clearing process, which is described in
12.4.7.5.3
SPTEF
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear
until it is serviced. SPTEF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI
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